Re: [RFT PATCH, AVX512]: Implement scalar float->unsigned int truncations with AVX512F

[Uros Bizjak <ubizjak at gmail dot com>]

On Mon, May 21, 2018 at 4:53 PM, Uros Bizjak <ubizjak@gmail.com> wrote:
> Hello!
>
> Attached patch implements scalar float->unsigned int truncations with AVX512F.
>
> 2018-05-21  Uros Bizjak  <ubizjak@gmail.com>
>
>     * config/i386/i386.md (fixuns_trunc<mode>di2): New insn pattern.
>     (fixuns_trunc<mode>si2_avx512f): Ditto.
>     (*fixuns_trunc<mode>si2_avx512f_zext): Ditto.
>     (fixuns_trunc<mode>si2): Also enable for AVX512F and TARGET_SSE_MATH.
>     Emit fixuns_trunc<mode>si2_avx512f for AVX512F targets.
>
> testsuite/ChangeLog:
>
> 2018-05-21  Uros Bizjak  <ubizjak@gmail.com>
>
>     * gcc.target/i386/cvt-2.c: New test.
>
> Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
>
> Unfortunately, I have to means to test the patch on AVX512 target, so
> to avoid some hidden issue, I'd like to ask someone to test it on live
> target.

Ops, ssemodesuffix handling was missing in the insn mnemonic. Fixed in
the attached v-2 patch.

Uros.

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