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Re: [PATCH][AArch64] Set SLOW_BYTE_ACCESS
- From: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>, James Greenhalgh <James dot Greenhalgh at arm dot com>
- Cc: nd <nd at arm dot com>
- Date: Tue, 15 May 2018 13:24:54 +0000
- Subject: Re: [PATCH][AArch64] Set SLOW_BYTE_ACCESS
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From: Wilco Dijkstra
Sent: 17 November 2017 15:21
To: GCC Patches
Cc: nd
Subject: [PATCH][AArch64] Set SLOW_BYTE_ACCESS
Contrary to all documentation, SLOW_BYTE_ACCESS simply means accessing
bitfields by their declared type, which results in better codegeneration on practically
any target.
I'm thinking we should completely remove all trace of SLOW_BYTE_ACCESS
from GCC as it's confusing and useless.
OK for commit until we get rid of it?
ChangeLog:
2017-11-17 Wilco Dijkstra <wdijkstr@arm.com>
gcc/
* config/aarch64/aarch64.h (SLOW_BYTE_ACCESS): Set to 1.
--
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 056110afb228fb919e837c04aa5e5552a4868ec3..d8f4d129a02fb89eb00d256aba8c4764d6026078 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -769,14 +769,9 @@ typedef struct
if given data not on the nominal alignment. */
#define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
-/* Define this macro to be non-zero if accessing less than a word of
- memory is no faster than accessing a word of memory, i.e., if such
- accesses require more than one instruction or if there is no
- difference in cost.
- Although there's no difference in instruction count or cycles,
- in AArch64 we don't want to expand to a sub-word to a 64-bit access
- if we don't have to, for power-saving reasons. */
-#define SLOW_BYTE_ACCESS 0
+/* Contrary to all documentation, this enables wide bitfield accesses,
+ which results in better code when accessing multiple bitfields. */
+#define SLOW_BYTE_ACCESS 1
#define NO_FUNCTION_CSE 1