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Re: [PATCH PR81228][AARCH64] Fix ICE by adding LTGT in vec_cmp<mode><v_int_equiv>


On 14/12/17 10:38, Sudakshina Das wrote:
Hi

On 13/12/17 16:56, James Greenhalgh wrote:
On Wed, Dec 13, 2017 at 04:45:33PM +0000, Sudi Das wrote:
On 13/12/17 16:42, Sudakshina Das wrote:
Hi

This patch is a follow up to the existing discussions on
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01904.html
Bin had earlier submitted a patch to fix the ICE that occurs because of
the missing LTGT in aarch64-simd.md.
That discussion opened up a new bug report PR81647 for an inconsistent
behavior.

As discussed earlier on the gcc-patches discussion and on the bug
report, PR81647 was occurring because of how UNEQ was handled in
aarch64-simd.md rather than LTGT. Since __builtin_islessgreater is
guaranteed to not give an FP exception but LTGT might,
__builtin_islessgreater gets converted to ~UNEQ very early on in
fold_builtin_unordered_cmp. Thus I will post a separate patch for
correcting how UNEQ and other unordered comparisons are handled in
aarch64-simd.md.

This patch is only adding the missing LTGT to plug the ICE.

Testing done: Checked for regressions on bootstrapped
aarch64-none-linux-gnu and added a new compile time test case that gives
out LTGT to make sure it doesn't ICE.

Is this ok for trunk?

OK.

Thanks,
James


Thanks for the review.
Committed as r255625.
I think this needs a back-port as well to gcc-7-branch. Is that ok?

Sudi

Backport Ping!

Sudi


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