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Re: [PATCH 09/10] [ARC] Update (u)maddsidi patterns.


* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2017-11-27 12:09:58 +0100]:

> From: claziss <claziss@synopsys.com>
> 
> The accumulator registers are freely used by the compiler. However,
> there are a number of instructions which are having an intrinsic use
> of these registers. Update patterns to inform the compiler which ones.
> 
> gcc/
> 2017-09-19  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.md (maddsidi4, maddsidi4_split): Update pattern.
> 	(umaddsidi4,umaddsidi4): Likewise.
> 
> gcc/testsuite
> 2017-09-19  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* gcc.target/arc/tumaddsidi4.c: New test.

Looks good.

Thanks,
Andrew


> ---
>  gcc/config/arc/arc.md                      | 32 ++++++++++++++++++++++++++----
>  gcc/testsuite/gcc.target/arc/tumaddsidi4.c | 14 +++++++++++++
>  2 files changed, 42 insertions(+), 4 deletions(-)
>  create mode 100755 gcc/testsuite/gcc.target/arc/tumaddsidi4.c
> 
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index 42c6a23..155ee6c 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -6175,13 +6175,25 @@ archs4xd, archs4xd_slow, core_3"
>    [(set_attr "length" "0")])
>  
>  ;; MAC and DMPY instructions
> -(define_insn_and_split "maddsidi4"
> +(define_expand "maddsidi4"
> +  [(match_operand:DI 0 "register_operand" "")
> +   (match_operand:SI 1 "register_operand" "")
> +   (match_operand:SI 2 "extend_operand"   "")
> +   (match_operand:DI 3 "register_operand" "")]
> +  "TARGET_PLUS_DMPY"
> +  "{
> +   emit_insn (gen_maddsidi4_split (operands[0], operands[1], operands[2], operands[3]));
> +   DONE;
> +  }")
> +
> +(define_insn_and_split "maddsidi4_split"
>    [(set (match_operand:DI 0 "register_operand" "=r")
>  	(plus:DI
>  	 (mult:DI
>  	  (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
>  	  (sign_extend:DI (match_operand:SI 2 "extend_operand" "ri")))
> -	 (match_operand:DI 3 "register_operand" "r")))]
> +	 (match_operand:DI 3 "register_operand" "r")))
> +   (clobber (reg:DI ARCV2_ACC))]
>    "TARGET_PLUS_DMPY"
>    "#"
>    "TARGET_PLUS_DMPY && reload_completed"
> @@ -6263,13 +6275,25 @@ archs4xd, archs4xd_slow, core_3"
>     (set_attr "predicable" "no")
>     (set_attr "cond" "nocond")])
>  
> -(define_insn_and_split "umaddsidi4"
> +(define_expand "umaddsidi4"
> +  [(match_operand:DI 0 "register_operand" "")
> +   (match_operand:SI 1 "register_operand" "")
> +   (match_operand:SI 2 "extend_operand"   "")
> +   (match_operand:DI 3 "register_operand" "")]
> +  "TARGET_PLUS_DMPY"
> +  "{
> +   emit_insn (gen_umaddsidi4_split (operands[0], operands[1], operands[2], operands[3]));
> +   DONE;
> +  }")
> +
> +(define_insn_and_split "umaddsidi4_split"
>    [(set (match_operand:DI 0 "register_operand" "=r")
>  	(plus:DI
>  	 (mult:DI
>  	  (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
>  	  (zero_extend:DI (match_operand:SI 2 "extend_operand" "ri")))
> -	 (match_operand:DI 3 "register_operand" "r")))]
> +	 (match_operand:DI 3 "register_operand" "r")))
> +   (clobber (reg:DI ARCV2_ACC))]
>    "TARGET_PLUS_DMPY"
>    "#"
>    "TARGET_PLUS_DMPY && reload_completed"
> diff --git a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c
> new file mode 100755
> index 0000000..40d2b33
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mcpu=archs -O1 -mmpy-option=plus_dmpy" } */
> +
> +/* Check how we generate umaddsidi4 patterns.  */
> +long a;
> +long long b;
> +unsigned c, d;
> +
> +void fn1(void)
> +{
> +  b = d * (long long)c + a;
> +}
> +
> +/* { dg-final { scan-assembler "macu 0,r" } } */
> -- 
> 1.9.1
> 


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