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Re: [patch][x86] GFNI enabling [2/4]
- From: Jakub Jelinek <jakub at redhat dot com>
- To: "Koval, Julia" <julia dot koval at intel dot com>
- Cc: Kirill Yukhin <kirill dot yukhin at gmail dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 31 Oct 2017 20:27:48 +0100
- Subject: Re: [patch][x86] GFNI enabling [2/4]
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- Reply-to: Jakub Jelinek <jakub at redhat dot com>
On Mon, Oct 30, 2017 at 07:02:23PM +0000, Koval, Julia wrote:
> gcc/testsuite/
> * gcc.target/i386/avx-1.c: Handle new intrinsics.
> * gcc.target/i386/avx512-check.h: Check GFNI bit.
> * gcc.target/i386/avx512f-gf2p8affineinvqb-2.c: Runtime test.
> * gcc.target/i386/avx512vl-gf2p8affineinvqb-2.c: Runtime test.
> * gcc.target/i386/gfni-1.c: New.
> * gcc.target/i386/gfni-2.c: New.
> * gcc.target/i386/gfni-3.c: New.
> * gcc.target/i386/gfni-4.c: New.
The gfni-4.c testcase ICEs on i686-linux (e.g. try
make check-gcc RUNTESTFLAGS='--target_board=unix\{-m32/-msse,-m32/-mno-sse,-m64\} i386.exp=gfni*'
to see it).
I must say I'm confused by the CPUIDs, the https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
lists GFNI; 2x AVX+GFNI; 2x AVX512VL+GFNI; AVX512F+GFNI CPUIDs for the
instructions, but i386-builtins.def has:
BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v64qi, "__builtin_ia32_vgf2p8affineinvqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEINVQB512, UNKNOWN
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v64qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v64qi_mask", IX86_
BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v32qi, "__builtin_ia32_vgf2p8affineinvqb_v32qi", IX86_BUILTIN_VGF2P8AFFINEINVQB256, UNKNOWN
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v32qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_
BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v16qi, "__builtin_ia32_vgf2p8affineinvqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN
BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v16qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_
and the gfniintrin.h requires just gfni for the first insn,
and then some combinations of gfni,avx, or gfni,avx512vl, or
gfni,avx512vl,avx512bw, or gfni,avx512f,avx512bw.
So, what is right, the paper, i386-builtins.def or gfniintrin.h?
Obviously even if the GF2P8AFFINEINVQB instruction doesn't list SSE as
required CPUID, we can't really emit it without at least SSE because
then the operands can't be emitted. So, at least in GCC we should
require both GFNI and SSE for the first instruction.
Which leads to another issue, as ix86_expand_builtin documents,
we treat the BDESC ISAs OPTION_MASK_ISA_ISA1 | OPTION_MASK_ISA_ISA2
as either ISA1 or ISA2, not ISA1 and ISA2. The exceptions are
MMX, AVX512VL and 64BIT is also special.
So, shall GFNI be added to that set? Do we have other ISAs that
should be handled the same? I guess maybe OPTION_MASK_ISA_AES, but
that is handled weirdly.
Jakub