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Re: [PATCH, i386] Enable option -mprefer-avx256 added for Intel AVX512 configuration
- From: Markus Trippelsdorf <markus at trippelsdorf dot de>
- To: Jakub Jelinek <jakub at redhat dot com>
- Cc: "Shalnov, Sergey" <sergey dot shalnov at intel dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, "ubizjak at gmail dot com" <ubizjak at gmail dot com>, "kirill dot yukhin at gmail dot com" <kirill dot yukhin at gmail dot com>, "Koval, Julia" <julia dot koval at intel dot com>, "Senkevich, Andrew" <andrew dot senkevich at intel dot com>
- Date: Thu, 14 Sep 2017 15:18:08 +0200
- Subject: Re: [PATCH, i386] Enable option -mprefer-avx256 added for Intel AVX512 configuration
- Authentication-results: sourceware.org; auth=none
- References: <71475DE127B5E94A8E189586234C0888122723D7@irsmsx105.ger.corp.intel.com> <20170914123616.GI1701@tucnak>
On 2017.09.14 at 14:36 +0200, Jakub Jelinek wrote:
> On Thu, Sep 14, 2017 at 12:10:50PM +0000, Shalnov, Sergey wrote:
> > GCC has the option "mprefer-avx128" to use 128-bit AVX registers instead
> > of 256-bit AVX registers in the auto-vectorizer.
>
> > This patch enables the command line option "mprefer-avx256" that reduces
> > 512-bit registers usage in "march=skylake-avx512" mode. This is the
> > initial implementation of the option. Currently, 512-bit registers might
> > appears in some cases. I have a plan to continue fix the cases where
> > 512-bit registers are appear. Sergey
>
> What is the rationale for this? -mprefer-avx128 has been added because some
> (older) AMD CPUs implement AVX by performing 256-bit ops as two 128-bit uops
> and thus it is faster to emit 128-bit only code.
> Is that the case for any AVX512 implementations too?
You get a huge frequency drop when you run AVX512 code. There are
situations where this more than offsets the potential gains.
Glibc had to disable AVX512 memcpy because of this issue.
--
Markus