[AArch64] Merge stores of D register values of different modes

[Jackson Woodruff <jackson dot woodruff at foss dot arm dot com>]

Hi all,

This patch merges loads and stores from D-registers that are of 
different modes.

Code like this:

    typedef int __attribute__((vector_size(8))) vec;
    struct pair
    {
      vec v;
      double d;
    }

    void
    assign (struct pair *p, vec v)
    {
      p->v = v;
      p->d = 1.0;
    }

Now generates a stp instruction whereas previously it generated two 
`str` instructions. Likewise for loads.

I have taken the opportunity to merge some of the patterns into a single 
pattern. Previously, we had different patterns for DI, DF, SI, SF modes. 
The patch uses the new iterators to reduce these to two patterns.


This patch also merges storing of double zero values with
long integer values:

    struct pair
    {
      long long l;
      double d;
    }

    void
    foo (struct pair *p)
    {
      p->l = 10;
      p->d = 0.0;
    }

Now generates a single store pair instruction rather than two `str` 
instructions.

Bootstrap and testsuite run OK. OK for trunk?

Jackson

gcc/

2017-07-21  Jackson Woodruff  <jackson.woodruff@arm.com>

	* config/aarch64/aarch64.md: New patterns to generate stp
	and ldp.
	* config/aarch64/aarch64-ldpstp.md: Modified peephole
	for different mode ldpstp and added peephole for merge zero
	stores. Likewise for loads.
	* config/aarch64/aarch64.c (aarch64_operands_ok_for_ldpstp):
	Added size check.
	(aarch64_gen_store_pair): Rename calls to match new patterns.
	(aarch64_gen_load_pair): Rename calls to match new patterns.
	* config/aarch64/aarch64-simd.md (store_pair<mode>): Updated
	pattern to match two modes.
	(store_pair_sw, store_pair_dw): New patterns to generate stp for
	single words and double words.
	(load_pair_sw, load_pair_dw): Likewise.
	(store_pair_sf, store_pair_df, store_pair_si, store_pair_di):
	Removed.
	(load_pair_sf, load_pair_df, load_pair_si, load_pair_di):
	Removed.
	* config/aarch64/iterators.md: New mode iterators for
	types in d registers and duplicate DX and SX modes.
	New iterator for DI, DF, SI, SF.
	* config/aarch64/predicates.md (aarch64_reg_zero_or_fp_zero):
	New.


gcc/testsuite/

2017-07-21  Jackson Woodruff  <jackson.woodruff@arm.com>

	* gcc.target/aarch64/ldp_stp_6.c: New.
	* gcc.target/aarch64/ldp_stp_7.c: New.
	* gcc.target/aarch64/ldp_stp_8.c: New.

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