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RE: [PATCH] [Aarch64] Optimize subtract in shift counts
- From: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>, "kenner at vlsi1 dot ultra dot nyu dot edu" <kenner at vlsi1 dot ultra dot nyu dot edu>
- Cc: nd <nd at arm dot com>, Michael Collison <Michael dot Collison at arm dot com>, "pinskia at gmail dot com" <pinskia at gmail dot com>
- Date: Tue, 8 Aug 2017 10:04:17 +0000
- Subject: RE: [PATCH] [Aarch64] Optimize subtract in shift counts
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Richard Kenner wrote:
>Michael Collison wrote:
> > On Aarc64 SHIFT_COUNT_TRUNCATED is only true if SIMD code generation
> > is disabled. This is because the simd instructions can be used for
> > shifting but they do not truncate the shift count.
>
> In that case, the change isn't safe! Consider if the value was
> negative, for example. Yes, it's technically undefined, but I'm not
> sure I'd want to rely on that.
No it's perfectly safe - it becomes an integer-only shift after the split since it
keeps the masking as part of the pattern.
But generally the SHIFT_COUNT_TRUNCATED is a mess, and so are other ways
of doing this - note the extremely complex subregs in the patch, none of that should
be required as there are no QI registers on AArch64! So it would be great if there
was a better way to describe the number of bits used by a particular shift alternative.
Wilco