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[PATCH, rs6000] Fix for vec_mulo and vec_mule test case
- From: Carl Love <cel at us dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org, David Edelsohn <dje dot gcc at gmail dot com>, Segher Boessenkool <segher at kernel dot crashing dot org>
- Cc: Bill Schmidt <wschmidt at linux dot vnet dot ibm dot com>, cel at us dot ibm dot com
- Date: Thu, 22 Jun 2017 09:04:38 -0700
- Subject: [PATCH, rs6000] Fix for vec_mulo and vec_mule test case
- Authentication-results: sourceware.org; auth=none
GCC Maintainers:
Commit 249424 fixed the vec_mulo and vec_mule support however, the
changes for the test case did not get included in the previous patch.
The testing worked great for me as I had the fix. Not so good for
everyone else as I didn't share the test case fix with mainline. Sorry
for the omission in the previous patch.
I have tested the following fix on powerpc64le-unknown-linux-gnu
(Power 8 LE), powerpc64-unknown-linux-gnu(Power 8 BE),
powerpc64-unknown-linux-gnu (Power 7).
Is the fix OK for gcc mainline?
Carl Love
-------------------------------------------------------------------
gcc/testsuite/ChangeLog:
2017-06-23 Carl Love <cel@us.ibm.com>
* gcc.target/powerpc/builtins-3.c (vmulosh, vmulouh, vmulesh,
vmuleuh): Fix scan-assembler-times should check for word not half word
instructions.
---
gcc/testsuite/gcc.target/powerpc/builtins-3.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-3.c b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
index b252488..00fa6ec 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-3.c
@@ -207,10 +207,10 @@ test_vul_sldw_vul_vul (vector unsigned long long x,
test_vsll_slo_vsll_vuc 1 vslo
test_vull_slo_vsll_vsc 1 vslo
test_vull_slo_vsll_vuc 1 vslo
- test_vsll_mulo_vsi_vsi 1 vmulosh
- test_vull_mulo_vui_vui 1 vmulouh
- test_vsll_mule_vsi_vsi 1 vmulesh
- test_vull_mule_vui_vui 1 vmuleuh
+ test_vsll_mulo_vsi_vsi 1 vmulosw
+ test_vull_mulo_vui_vui 1 vmulouw
+ test_vsll_mule_vsi_vsi 1 vmulesw
+ test_vull_mule_vui_vui 1 vmuleuw
test_vsc_mulo_vsc_vsc 1 xxsldwi
test_vuc_mulo_vuc_vuc 1 xxsldwi
test_vssi_mulo_vssi_vssi 1 xxsldwi
@@ -236,8 +236,8 @@ test_vul_sldw_vul_vul (vector unsigned long long x,
/* { dg-final { scan-assembler-times "xvnegsp" 1 } } */
/* { dg-final { scan-assembler-times "xvnegdp" 1 } } */
/* { dg-final { scan-assembler-times "vslo" 4 } } */
-/* { dg-final { scan-assembler-times "vmulosh" 1 } } */
-/* { dg-final { scan-assembler-times "vmulouh" 1 } } */
-/* { dg-final { scan-assembler-times "vmulesh" 1 } } */
-/* { dg-final { scan-assembler-times "vmuleuh" 1 } } */
+/* { dg-final { scan-assembler-times "vmulosw" 1 } } */
+/* { dg-final { scan-assembler-times "vmulouw" 1 } } */
+/* { dg-final { scan-assembler-times "vmulesw" 1 } } */
+/* { dg-final { scan-assembler-times "vmuleuw" 1 } } */
/* { dg-final { scan-assembler-times "xxsldwi" 8 } } */
--
1.9.1