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[PATCH 12/14] rs6000: Remove SPE high registers
Now we can remove the SPE high registers.
2017-06-06 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/darwin.h (REGISTER_NAMES): Delete the SPE high
registers.
* config/rs6000/rs6000.c (rs6000_reg_names, alt_reg_names): Ditto.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Change from 149
to 117.
(DWARF_REG_TO_UNWIND_COLUMN): Do not define.
(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS):
Delete the SPE high registers.
(REG_ALLOC_ORDER): Ditto.
(enum reg_class): Remove SPE_HIGH_REGS.
(REG_CLASS_NAMES): Ditto.
(REG_CLASS_CONTENTS): Delete the SPE high registers.
(REGISTER_NAMES): Ditto.
(rs6000_reg_names): Ditto.
* doc/tm.texi.in: Remove SPE as example.
* doc/tm.texi: Regenerate.
---
gcc/config/rs6000/darwin.h | 6 +--
gcc/config/rs6000/rs6000.c | 14 +-----
gcc/config/rs6000/rs6000.h | 122 ++++++++++-----------------------------------
gcc/doc/tm.texi | 2 -
gcc/doc/tm.texi.in | 2 -
5 files changed, 30 insertions(+), 116 deletions(-)
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 61e5e83..2422f25 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -194,11 +194,7 @@ extern int darwin_emit_branch_islands;
"vrsave", "vscr", \
"spe_acc", "spefscr", \
"sfp", \
- "tfhar", "tfiar", "texasr", \
- "rh0", "rh1", "rh2", "rh3", "rh4", "rh5", "rh6", "rh7", \
- "rh8", "rh9", "rh10", "rh11", "rh12", "rh13", "rh14", "rh15", \
- "rh16", "rh17", "rh18", "rh19", "rh20", "rh21", "rh22", "rh23", \
- "rh24", "rh25", "rh26", "rh27", "rh28", "rh29", "rh30", "rh31" \
+ "tfhar", "tfiar", "texasr" \
}
/* This outputs NAME to FILE. */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 89f9fc2..426400c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1478,12 +1478,7 @@ char rs6000_reg_names[][8] =
/* Soft frame pointer. */
"sfp",
/* HTM SPR registers. */
- "tfhar", "tfiar", "texasr",
- /* SPE High registers. */
- "0", "1", "2", "3", "4", "5", "6", "7",
- "8", "9", "10", "11", "12", "13", "14", "15",
- "16", "17", "18", "19", "20", "21", "22", "23",
- "24", "25", "26", "27", "28", "29", "30", "31"
+ "tfhar", "tfiar", "texasr"
};
#ifdef TARGET_REGNAMES
@@ -1511,12 +1506,7 @@ static const char alt_reg_names[][8] =
/* Soft frame pointer. */
"sfp",
/* HTM SPR registers. */
- "tfhar", "tfiar", "texasr",
- /* SPE High registers. */
- "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
- "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
- "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
- "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
+ "tfhar", "tfiar", "texasr"
};
#endif
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index da3b877..a154c5d 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1017,7 +1017,7 @@ enum data_align { align_abi, align_opt, align_both };
The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
-#define FIRST_PSEUDO_REGISTER 149
+#define FIRST_PSEUDO_REGISTER 117
/* This must be included for pre gcc 3.0 glibc compatibility. */
#define PRE_GCC3_DWARF_FRAME_REGISTERS 77
@@ -1026,16 +1026,6 @@ enum data_align { align_abi, align_opt, align_both };
aren't included in DWARF_FRAME_REGISTERS. */
#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
-/* The SPE has an additional 32 synthetic registers, with DWARF debug
- info numbering for these registers starting at 1200. While eh_frame
- register numbering need not be the same as the debug info numbering,
- we choose to number these regs for eh_frame at 1200 too.
-
- We must map them here to avoid huge unwinder tables mostly consisting
- of unused space. */
-#define DWARF_REG_TO_UNWIND_COLUMN(r) \
- ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
-
/* Use standard DWARF numbering for DWARF debugging information. */
#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
@@ -1066,10 +1056,7 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
- , 1, 1, 1, 1, 1, 1, \
- /* SPE High registers. */ \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
+ , 1, 1, 1, 1, 1, 1 \
}
/* 1 for registers not available across function calls.
@@ -1089,10 +1076,7 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1 \
- , 1, 1, 1, 1, 1, 1, \
- /* SPE High registers. */ \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
+ , 1, 1, 1, 1, 1, 1 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -1111,10 +1095,7 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0 \
- , 0, 0, 0, 0, 0, 0, \
- /* SPE High registers. */ \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
+ , 0, 0, 0, 0, 0, 0 \
}
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -1198,10 +1179,7 @@ enum data_align { align_abi, align_opt, align_both };
96, 95, 94, 93, 92, 91, \
108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
109, 110, \
- 111, 112, 113, 114, 115, 116, \
- 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \
- 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \
- 141, 142, 143, 144, 145, 146, 147, 148 \
+ 111, 112, 113, 114, 115, 116 \
}
/* True if register is floating-point. */
@@ -1439,7 +1417,6 @@ enum reg_class
CR_REGS,
NON_FLOAT_REGS,
CA_REGS,
- SPE_HIGH_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
@@ -1471,7 +1448,6 @@ enum reg_class
"CR_REGS", \
"NON_FLOAT_REGS", \
"CA_REGS", \
- "SPE_HIGH_REGS", \
"ALL_REGS" \
}
@@ -1482,51 +1458,49 @@ enum reg_class
#define REG_CLASS_CONTENTS \
{ \
/* NO_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
/* BASE_REGS. */ \
- { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
+ { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, \
/* GENERAL_REGS. */ \
- { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
+ { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, \
/* FLOAT_REGS. */ \
- { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
/* ALTIVEC_REGS. */ \
- { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \
/* VSX_REGS. */ \
- { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \
+ { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \
/* VRSAVE_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
/* VSCR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \
/* SPE_ACC_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, \
/* SPEFSCR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
/* SPR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
/* NON_SPECIAL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \
+ { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, \
/* LINK_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \
/* CTR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \
/* LINK_OR_CTR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \
/* SPECIAL_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \
/* SPEC_OR_GEN_REGS. */ \
- { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \
+ { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, \
/* CR0_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \
/* CR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \
+ { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \
/* NON_FLOAT_REGS. */ \
- { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \
+ { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, \
/* CA_REGS. */ \
- { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \
- /* SPE_HIGH_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \
+ { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \
/* ALL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \
+ { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } \
}
/* The same information, inverted:
@@ -2461,39 +2435,6 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
&rs6000_reg_names[114][0], /* tfhar */ \
&rs6000_reg_names[115][0], /* tfiar */ \
&rs6000_reg_names[116][0], /* texasr */ \
- \
- &rs6000_reg_names[117][0], /* SPE rh0. */ \
- &rs6000_reg_names[118][0], /* SPE rh1. */ \
- &rs6000_reg_names[119][0], /* SPE rh2. */ \
- &rs6000_reg_names[120][0], /* SPE rh3. */ \
- &rs6000_reg_names[121][0], /* SPE rh4. */ \
- &rs6000_reg_names[122][0], /* SPE rh5. */ \
- &rs6000_reg_names[123][0], /* SPE rh6. */ \
- &rs6000_reg_names[124][0], /* SPE rh7. */ \
- &rs6000_reg_names[125][0], /* SPE rh8. */ \
- &rs6000_reg_names[126][0], /* SPE rh9. */ \
- &rs6000_reg_names[127][0], /* SPE rh10. */ \
- &rs6000_reg_names[128][0], /* SPE rh11. */ \
- &rs6000_reg_names[129][0], /* SPE rh12. */ \
- &rs6000_reg_names[130][0], /* SPE rh13. */ \
- &rs6000_reg_names[131][0], /* SPE rh14. */ \
- &rs6000_reg_names[132][0], /* SPE rh15. */ \
- &rs6000_reg_names[133][0], /* SPE rh16. */ \
- &rs6000_reg_names[134][0], /* SPE rh17. */ \
- &rs6000_reg_names[135][0], /* SPE rh18. */ \
- &rs6000_reg_names[136][0], /* SPE rh19. */ \
- &rs6000_reg_names[137][0], /* SPE rh20. */ \
- &rs6000_reg_names[138][0], /* SPE rh21. */ \
- &rs6000_reg_names[139][0], /* SPE rh22. */ \
- &rs6000_reg_names[140][0], /* SPE rh22. */ \
- &rs6000_reg_names[141][0], /* SPE rh24. */ \
- &rs6000_reg_names[142][0], /* SPE rh25. */ \
- &rs6000_reg_names[143][0], /* SPE rh26. */ \
- &rs6000_reg_names[144][0], /* SPE rh27. */ \
- &rs6000_reg_names[145][0], /* SPE rh28. */ \
- &rs6000_reg_names[146][0], /* SPE rh29. */ \
- &rs6000_reg_names[147][0], /* SPE rh30. */ \
- &rs6000_reg_names[148][0], /* SPE rh31. */ \
}
/* Table of additional register names to use in user input. */
@@ -2550,15 +2491,6 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
{"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
/* Transactional Memory Facility (HTM) Registers. */ \
{"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \
- /* SPE high registers. */ \
- {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \
- {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \
- {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \
- {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \
- {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \
- {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \
- {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \
- {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \
}
/* This is how to output an element of a case-vector that is relative. */
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 2790dd6..39302f3 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -3569,8 +3569,6 @@ Define this macro if the target's representation for dwarf registers
is different than the internal representation for unwind column.
Given a dwarf register, this macro should return the internal unwind
column number to use instead.
-
-See the PowerPC's SPE target for an example.
@end defmac
@defmac DWARF_FRAME_REGNUM (@var{regno})
diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index dff6cf8..98f2e6b 100644
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -3129,8 +3129,6 @@ Define this macro if the target's representation for dwarf registers
is different than the internal representation for unwind column.
Given a dwarf register, this macro should return the internal unwind
column number to use instead.
-
-See the PowerPC's SPE target for an example.
@end defmac
@defmac DWARF_FRAME_REGNUM (@var{regno})
--
1.9.3