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Re: [PATCH][AArch64] Add HF vector modes to lane-to-lane INS pattern
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <marcus dot shawcroft at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, <nd at arm dot com>
- Date: Fri, 2 Jun 2017 14:53:27 +0100
- Subject: Re: [PATCH][AArch64] Add HF vector modes to lane-to-lane INS pattern
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On Fri, Apr 21, 2017 at 09:34:20AM +0100, Kyrill Tkachov wrote:
> Hi all,
>
> For the testcase in the patch we currently miss a combination and generate:
> foo:
> dup h1, v1.h[2]
> ins v0.h[3], v1.h[0]
> ret
>
> bar:
> dup h1, v1.h[2]
> ins v0.h[3], v1.h[0]
> ret
>
> This is because the *aarch64_simd_vec_copy_lane<mode> pattern is not defined
> for HF vector modes. I think that's just a simple oversight fixed by using
> the VALL_F16 mode iterator instead of VALL (it just adds V4HF and V8HF on top of VALL)
> and we can use the proper INS pattern and generate:
> foo:
> ins v0.h[3], v1.h[2]
> ret
>
> bar:
> ins v0.h[3], v1.h[2]
> ret
>
> Bootstrapped and tested on aarch64-none-linux-gnu.
> Ok for GCC 8?
Yes, this is OK.
Thanks,
James
>
> Thanks,
> Kyrill
>
> 2017-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
>
> * config/aarch64/aarch64-simd.md (*aarch64_simd_vec_copy_lane<mode>):
> Use VALL_F16 iterator rather than VALL.
>
> 2017-04-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
>
> * gcc.target/aarch64/hfmode_ins_1.c: New test.
>