[PATCH, i386]: Handle variable shifts in STV pass (PR 70799)

[Uros Bizjak <ubizjak at gmail dot com>]

Hello!

Attached patch adds handling of variable shifts in STV pass. The patch
detects when we are processing QImode count register of a scalar shift
instruction, and zero-extends it from QImode to DImode, either from
scalar register or vector register. The extension is necessary, since
scalar shifts operate with QImode value, where vector shifts truncate
shifts using DImode value from count register.

When the compiler is bootstrapped with --with-arch=corei7-avx
--with-cpu=corei7-avx, there are quite some vector shifts generated in
32bit libraries.

2017-04-23  Uros Bizjak  <ubizjak@gmail.com>

    PR target/70799
    * config/i386/i386.c (dimode_scalar_to_vector_candidate_p)
    <case ASHIFT, case LSHIFTRT>: Also consider variable shifts.
    Check "XEXP (src, 1)" operand here.
    <case PLUS, case MINUS, case IOR, case XOR, case AND>:
    Check "XEXP (src, 1)" operand here.
    (dimode_scalar_chain::make_vector_copies): Detect count register
    of a shift instruction.  Zero extend count register from QImode
    to DImode to satisfy vector shift pattern count operand predicate.
    Substitute vector shift count operand with a DImode copy.
    (dimode_scalar_chain::convert_reg): Ditto, zero-extend from
    vector register.

testsuite/ChangeLog:

2017-04-23  Uros Bizjak  <ubizjak@gmail.com>

    PR target/70799
    * gcc.target/i386/pr70799-4.c: New test.

Patch was bootstrapped and regression tested on x86_64-linux-gnu
{,-m32}, configured with --with-arch=corei7-avx --with-cpu=corei7-avx.

Attachment: p.diff.txt
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