This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH][AArch64] Implement ALU_BRANCH fusion
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: "Hurugalawadi, Naveen" <Naveen dot Hurugalawadi at cavium dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, "Pinski, Andrew" <Andrew dot Pinski at cavium dot com>, Marcus Shawcroft <marcus dot shawcroft at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, <nd at arm dot com>
- Date: Wed, 8 Mar 2017 18:04:00 +0000
- Subject: Re: [PATCH][AArch64] Implement ALU_BRANCH fusion
- Authentication-results: sourceware.org; auth=none
- Authentication-results: spf=pass (sender IP is 217.140.96.140) smtp.mailfrom=arm.com; cavium.com; dkim=none (message not signed) header.d=none;cavium.com; dmarc=bestguesspass action=none header.from=arm.com;
- Nodisclaimer: True
- References: <CO2PR07MB2694CB39F815C51139D35101832C0@CO2PR07MB2694.namprd07.prod.outlook.com>
- Spamdiagnosticmetadata: NSPM
- Spamdiagnosticoutput: 1:99
On Mon, Mar 06, 2017 at 05:10:10AM +0000, Hurugalawadi, Naveen wrote:
> Hi,
>
> Please find attached the patch that implements alu_branch fusion
> for AArch64.
> The patch doesn't change spec but improve other benchmarks.
>
> Bootstrapped and Regression tested on aarch64-thunder-linux.
> Please review the patch and let us know if its okay for Stage-1?
This description is insufficient for me to review this patch - in
particular I'd need more detail on what types of instruction pairs you
are trying to fuse. From inspection you will be trying to fuse any
ALU operation with an unconditional direct branch. Is that what you
intend?
i.e. you are looking to fuse instruction sequences like:
add x0, x1, #5
b .L3
csel x0, x1, x1, gt
b .L4
Have I understood that right?
> + if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH)
> + && any_uncondjump_p (curr))
> + {
> + /* These types correspond to the reservation "vulcan_alu_basic" for
> + Broadcom Vulcan: these are ALU operations that produce a single uop
> + during instruction decoding. */
This comment looks incorrect - there is no vulcan_alu_basic reservation
in trunk GCC.
Thanks,
James