+
+/* Return the next set bit in BMP from START onwards. Return the total number
+ of bits in BMP if no set bit is found at or after START. */
+
+static unsigned int
+aarch64_get_next_set_bit (sbitmap bmp, unsigned int start)
+{
+ unsigned int nbits = SBITMAP_SIZE (bmp);
+ if (start == nbits)
+ return start;
+
+ gcc_assert (start < nbits);
+ for (unsigned int i = start; i < nbits; i++)
+ if (bitmap_bit_p (bmp, i))
+ return i;
+
+ return nbits;
+}
+
+/* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
+
+static void
+aarch64_emit_prologue_components (sbitmap components)
+{
+ rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
+ ? HARD_FRAME_POINTER_REGNUM
+ : STACK_POINTER_REGNUM);
+
+ unsigned total_bits = SBITMAP_SIZE (components);
Would this be clearer called last_regno ?
+ unsigned regno = aarch64_get_next_set_bit (components, R0_REGNUM);
+ rtx_insn *insn = NULL;
+
+ while (regno != total_bits)
+ {
+ machine_mode mode = GP_REGNUM_P (regno) ? DImode : DFmode;
Comment about why this can be DFmode rather than some 128-bit mode might
be useful here.
+ rtx reg = gen_rtx_REG (mode, regno);
+ HOST_WIDE_INT offset = cfun->machine->frame.reg_offset[regno];
+ if (!frame_pointer_needed)
+ offset += cfun->machine->frame.frame_size
+ - cfun->machine->frame.hard_fp_offset;
+ rtx addr = plus_constant (Pmode, ptr_reg, offset);
+ rtx mem = gen_frame_mem (mode, addr);
+
+ rtx set = gen_rtx_SET (mem, reg);
+ unsigned regno2 = aarch64_get_next_set_bit (components, regno + 1);
+ /* No more registers to save after REGNO.
+ Emit a single save and exit. */
+ if (regno2 == total_bits)
+ {
+ insn = emit_insn (set);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set));
+ break;
+ }
+
+ HOST_WIDE_INT offset2 = cfun->machine->frame.reg_offset[regno2];
+ /* The next register is not of the same class or its offset is not
+ mergeable with the current one into a pair. */
+ if (!satisfies_constraint_Ump (mem)
+ || GP_REGNUM_P (regno) != GP_REGNUM_P (regno2)
+ || (offset2 - cfun->machine->frame.reg_offset[regno])
+ != GET_MODE_SIZE (DImode))
+ {
+ insn = emit_insn (set);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_OFFSET, copy_rtx (set));
+
+ regno = regno2;
+ continue;
+ }
+
+ /* REGNO2 can be stored in a pair with REGNO. */
+ rtx reg2 = gen_rtx_REG (mode, regno2);
+ if (!frame_pointer_needed)
+ offset2 += cfun->machine->frame.frame_size
+ - cfun->machine->frame.hard_fp_offset;
+ rtx addr2 = plus_constant (Pmode, ptr_reg, offset2);
+ rtx mem2 = gen_frame_mem (mode, addr2);
+ rtx set2 = gen_rtx_SET (mem2, reg2);
+
+ insn = emit_insn (aarch64_gen_store_pair (mode, mem, reg, mem2, reg2));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_OFFSET, set);
+ add_reg_note (insn, REG_CFA_OFFSET, set2);
+
+ regno = aarch64_get_next_set_bit (components, regno2 + 1);
+ }
+
+}
+
+/* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
+
+static void
+aarch64_emit_epilogue_components (sbitmap components)
Given the similarity of the logic, is there any way you can refactor this
with the prologue code above?
+{
+
+ rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
+ ? HARD_FRAME_POINTER_REGNUM
+ : STACK_POINTER_REGNUM);
+ unsigned total_bits = SBITMAP_SIZE (components);
+ unsigned regno = aarch64_get_next_set_bit (components, R0_REGNUM);
+ rtx_insn *insn = NULL;
+
+ while (regno != total_bits)
+ {
+ machine_mode mode = GP_REGNUM_P (regno) ? DImode : DFmode;
+ rtx reg = gen_rtx_REG (mode, regno);
+ HOST_WIDE_INT offset = cfun->machine->frame.reg_offset[regno];
+ if (!frame_pointer_needed)
+ offset += cfun->machine->frame.frame_size
+ - cfun->machine->frame.hard_fp_offset;
+ rtx addr = plus_constant (Pmode, ptr_reg, offset);
+ rtx mem = gen_frame_mem (mode, addr);
+
+ unsigned regno2 = aarch64_get_next_set_bit (components, regno + 1);
+ /* No more registers after REGNO to restore.
+ Emit a single restore and exit. */
+ if (regno2 == total_bits)
+ {
+ insn = emit_move_insn (reg, mem);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_RESTORE, reg);
+ break;
+ }
+
+ HOST_WIDE_INT offset2 = cfun->machine->frame.reg_offset[regno2];
+ /* The next register is not of the same class or its offset is not
+ mergeable with the current one into a pair or the offset doesn't fit
+ for a load pair. Emit a single restore and continue from REGNO2. */
+ if (!satisfies_constraint_Ump (mem)
+ || GP_REGNUM_P (regno) != GP_REGNUM_P (regno2)
+ || (offset2 - cfun->machine->frame.reg_offset[regno])
+ != GET_MODE_SIZE (DImode))
+ {
+ insn = emit_move_insn (reg, mem);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_RESTORE, reg);
+
+ regno = regno2;
+ continue;
+ }
+
+ /* REGNO2 can be loaded in a pair with REGNO. */
+ rtx reg2 = gen_rtx_REG (mode, regno2);
+ if (!frame_pointer_needed)
+ offset2 += cfun->machine->frame.frame_size
+ - cfun->machine->frame.hard_fp_offset;
+ rtx addr2 = plus_constant (Pmode, ptr_reg, offset2);
+ rtx mem2 = gen_frame_mem (mode, addr2);
+
+ insn = emit_insn (aarch64_gen_load_pair (mode, reg, mem, reg2, mem2));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_RESTORE, reg);
+ add_reg_note (insn, REG_CFA_RESTORE, reg2);
+
+ regno = aarch64_get_next_set_bit (components, regno2 + 1);
+ }
+}
+
+/* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
+
+static void
+aarch64_set_handled_components (sbitmap components)
+{
+ for (unsigned regno = R0_REGNUM; regno <= V31_REGNUM; regno++)
+ if (bitmap_bit_p (components, regno))
+ cfun->machine->reg_is_wrapped_separately[regno] = true;
+}
+
/* AArch64 stack frames generated by this compiler look like:
+-------------------------------+
@@ -3944,29 +4218,6 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x,
return false;
}
-bool
-aarch64_offset_7bit_signed_scaled_p (machine_mode mode, HOST_WIDE_INT offset)
-{
- return (offset >= -64 * GET_MODE_SIZE (mode)
- && offset < 64 * GET_MODE_SIZE (mode)
- && offset % GET_MODE_SIZE (mode) == 0);
-}
-
-static inline bool
-offset_9bit_signed_unscaled_p (machine_mode mode ATTRIBUTE_UNUSED,
- HOST_WIDE_INT offset)
-{
- return offset >= -256 && offset < 256;
-}
-
-static inline bool
-offset_12bit_unsigned_scaled_p (machine_mode mode, HOST_WIDE_INT offset)
-{
- return (offset >= 0
- && offset < 4096 * GET_MODE_SIZE (mode)
- && offset % GET_MODE_SIZE (mode) == 0);
-}
-
/* Return true if MODE is one of the modes for which we
support LDP/STP operations. */
@@ -14452,6 +14703,30 @@ aarch64_optab_supported_p (int op, machine_mode mode1, machine_mode,
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
aarch64_first_cycle_multipass_dfa_lookahead_guard
+#undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
+#define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
+ aarch64_get_separate_components
+
+#undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
+#define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
+ aarch64_components_for_bb
+
+#undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
+#define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
+ aarch64_disqualify_components
+
+#undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
+#define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
+ aarch64_emit_prologue_components
+
+#undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
+#define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
+ aarch64_emit_epilogue_components
+
+#undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
+#define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
+ aarch64_set_handled_components
+
#undef TARGET_TRAMPOLINE_INIT
#define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 584ff5c..fb89e5a 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -591,6 +591,8 @@ struct GTY (()) aarch64_frame
typedef struct GTY (()) machine_function
{
struct aarch64_frame frame;
+ /* One entry for each GPR and FP register. */
+ bool reg_is_wrapped_separately[V31_REGNUM + 1];
Another hardcoded use of V31_REGNUM.
Thanks,
James