Re: [PATCH] arc/nps400: New peephole2 pattern allow more cmem loads

[Andrew Burgess <andrew dot burgess at embecosm dot com>]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2016-11-17 13:02:02 +0000]:

> Hi Andrew,
> 
> Approved, please apply, but ...
> 
> > +(define_peephole2
> > +  [(set (match_operand:SI 0 "register_operand" "")
> > +        (sign_extend:SI
> > +          (match_operand:QI 1 "any_mem_operand" "")))
> > +   (set (reg:CC_ZN CC_REG)
> > +	(compare:CC_ZN (match_dup 0)
> > +                       (const_int 0)))
> > +   (set (pc)
> > +        (if_then_else (match_operator 2 "ge_lt_comparison_operator"
> > +                        [(reg:CC_ZN CC_REG) (const_int 0)])
> > +                      (match_operand 3 "" "")
> > +                      (match_operand 4 "" "")))]
> > +  "TARGET_NPS_CMEM
> > +   && cmem_address (XEXP (operands[1], 0), SImode)
> > +   && peep2_reg_dead_p (2, operands[0])
> > +   && peep2_regno_dead_p (3, CC_REG)"
> > +  [(set (match_dup 0)
> > +        (zero_extend:SI
> > +          (match_dup 1)))
> > +   (set (reg:CC_ZN CC_REG)
> > +	(compare:CC_ZN (zero_extract:SI
> > +                         (match_dup 0)
> > +                         (const_int 1)
> > +                         (const_int 7))
> > +                       (const_int 0)))
> > +   (set (pc)
> > +        (if_then_else (match_dup 2)
> > +                      (match_dup 3)
> > +                      (match_dup 4)))]
> > +  "if (GET_CODE (operands[2]) == GE)
> > +     operands[2] = gen_rtx_EQ (VOIDmode, gen_rtx_REG (CC_ZNmode, 61),
> > const0_rtx);
> > +   else
> > +     operands[2] = gen_rtx_NE (VOIDmode, gen_rtx_REG (CC_ZNmode, 61),
> > const0_rtx);")
> > +
> 
> It seems to me you use spaces instead of tabs.

Ooops.  I'll fix.

> 
> Note on tests: It will be nice to add a test where the added
> peephole kicks in. If you consider to add this test to the current
> patch, please resubmit it.

There were cmem-bit-{1,2,3,4}.c added in that patch.  All of which
fail for me without the peephole, and work with the peephole.

The code generated for L/E ARC is slightly different than the code
generated for B/E ARC due to how the structures are laid out in
memory, so, for now I've made parts of the test B/E only.

In order to get code that is as efficient for L/E as B/E I'd end up
adding a whole new peeophole, I'd rather not do that - it would be
extra code to maintain for a combination CMEM+L/E that is not used.  I
figure we can come back to that if/when that combination ever becomes
interesting.  I'm hoping you'll be fine with that.

Thanks,
Andrew