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[PATCH 1/2][AArch64] Add bfx attribute

From: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
To: GCC Patches <gcc-patches at gcc dot gnu dot org>
Cc: nd <nd at arm dot com>
Date: Thu, 10 Nov 2016 17:11:39 +0000
Subject: [PATCH 1/2][AArch64] Add bfx attribute
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Currently the SBFM, UBFM and BFM instructions all use the attribute "bfm".
SBFM and UBFM include all shifts on AArch64, which are simpler than bitfield
insert.  Add a new bfx attribute for these instructions so that they can be
modelled more accurately in the future.  There is no difference in code 
generation.

ChangeLog:
2016-11-10  Wilco Dijkstra  <wdijkstr@arm.com>

	* config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3)
	Use bfx attribute.
	(aarch64_lshr_sisd_or_int_<mode>3): Likewise.
	(aarch64_ashr_sisd_or_int_<mode>3): Likewise.
	(<optab>si3_insn_uxtw): Likewise.
	(<optab><mode>3_insn): Likewise.
	(<ANY_EXTEND:optab><GPI:mode>_ashl<SHORT:mode>): Likewise.
	(zero_extend<GPI:mode>_lshr<SHORT:mode>): Likewise.
	(extend<GPI:mode>_ashr<SHORT:mode>): Likewise.
	(<optab><mode>): Likewise.
	(insv<mode>): Likewise.
	(andim_ashift<mode>_bfiz): Likewise.
	* config/aarch64/thunderx.md (thunderx_shift): Add bfx.
	* config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.
	* config/arm/cortex-a57.md (cortex_a57_alu): Add bfx.
	* config/arm/exynos-m1.md (exynos_m1_alu): Add bfx.
	(exynos_m1_alu_p): Likewise.
	* config/arm/types.md: Add bfx.
	* config/arm/xgene1.md (xgene1_bfm): Add bfx.

--
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 62eda569f9b642ac569a61718d7debf7eae1b59e..afd463602af4c3f19db8f8cc834aa8cf0b78867e 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3955,7 +3955,7 @@
    shl\t%<rtn>0<vas>, %<rtn>1<vas>, %2
    ushl\t%<rtn>0<vas>, %<rtn>1<vas>, %<rtn>2<vas>"
   [(set_attr "simd" "no,no,yes,yes")
-   (set_attr "type" "bfm,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
+   (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>, neon_shift_reg<q>")]
 )
 
 ;; Logical right shift using SISD or Integer instruction
@@ -3972,7 +3972,7 @@
    #
    #"
   [(set_attr "simd" "no,no,yes,yes,yes")
-   (set_attr "type" "bfm,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
+   (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
 )
 
 (define_split
@@ -4019,7 +4019,7 @@
    #
    #"
   [(set_attr "simd" "no,no,yes,yes,yes")
-   (set_attr "type" "bfm,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
+   (set_attr "type" "bfx,shift_reg,neon_shift_imm<q>,neon_shift_reg<q>,neon_shift_reg<q>")]
 )
 
 (define_split
@@ -4129,7 +4129,7 @@
   "@
    <shift>\\t%w0, %w1, %2
    <shift>\\t%w0, %w1, %w2"
-  [(set_attr "type" "bfm,shift_reg")]
+  [(set_attr "type" "bfx,shift_reg")]
 )
 
 (define_insn "*<optab><mode>3_insn"
@@ -4141,7 +4141,7 @@
   operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
   return "<bfshift>\t%w0, %w1, %2, %3";
 }
-  [(set_attr "type" "bfm")]
+  [(set_attr "type" "bfx")]
 )
 
 (define_insn "*extr<mode>5_insn"
@@ -4234,7 +4234,7 @@
   operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
   return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
 }
-  [(set_attr "type" "bfm")]
+  [(set_attr "type" "bfx")]
 )
 
 (define_insn "*zero_extend<GPI:mode>_lshr<SHORT:mode>"
@@ -4247,7 +4247,7 @@
   operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
   return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3";
 }
-  [(set_attr "type" "bfm")]
+  [(set_attr "type" "bfx")]
 )
 
 (define_insn "*extend<GPI:mode>_ashr<SHORT:mode>"
@@ -4260,7 +4260,7 @@
   operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
   return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3";
 }
-  [(set_attr "type" "bfm")]
+  [(set_attr "type" "bfx")]
 )
 
 ;; -------------------------------------------------------------------
@@ -4283,7 +4283,7 @@
 			 (match_operand 3 "const_int_operand" "n")))]
   ""
   "<su>bfx\\t%<w>0, %<w>1, %3, %2"
-  [(set_attr "type" "bfm")]
+  [(set_attr "type" "bfx")]
 )
 
 ;; Bitfield Insert (insv)
@@ -4365,7 +4365,7 @@
 	      : GEN_INT (<GPI:sizen> - UINTVAL (operands[2]));
   return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
 }
-  [(set_attr "type" "bfm")]
+  [(set_attr "type" "bfx")]
 )
 
 ;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below
@@ -4377,7 +4377,7 @@
 		 (match_operand 3 "const_int_operand" "n")))]
   "aarch64_mask_and_shift_for_ubfiz_p (<MODE>mode, operands[3], operands[2])"
   "ubfiz\\t%<w>0, %<w>1, %2, %P3"
-  [(set_attr "type" "bfm")]
+  [(set_attr "type" "bfx")]
 )
 
 (define_insn "bswap<mode>2"
diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
index 058713a2ad98a364d36a3faaf0e93c39cb89adbc..7c1c28b0498cfe0129e3f0de7e29e31536fe421a 100644
--- a/gcc/config/aarch64/thunderx.md
+++ b/gcc/config/aarch64/thunderx.md
@@ -39,7 +39,7 @@
 
 (define_insn_reservation "thunderx_shift" 1
   (and (eq_attr "tune" "thunderx")
-       (eq_attr "type" "bfm,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
+       (eq_attr "type" "bfm,bfx,extend,rotate_imm,shift_imm,shift_reg,rbit,rev"))
   "thunderx_pipe0 | thunderx_pipe1")
 
 
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index 70c0f4daabe0ccb8e32808f1af51f5460e087a18..eb6d0b04976aaf441dd95cc43d02918226e75387 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -93,7 +93,7 @@
   (and (eq_attr "tune" "cortexa53")
        (eq_attr "type" "alu_shift_imm,alus_shift_imm,
 			crc,logic_shift_imm,logics_shift_imm,
-			alu_ext,alus_ext,bfm,extend,mvn_shift"))
+			alu_ext,alus_ext,bfm,bfx,extend,mvn_shift"))
   "cortex_a53_slot_any")
 
 (define_insn_reservation "cortex_a53_alu_shift_reg" 3
diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index 85b18e5970f6cbb4f11e76d7f461a9a548fc7ce2..da461846baa5b28ce3d9c9f731dbfd7becb31a85 100644
--- a/gcc/config/arm/cortex-a57.md
+++ b/gcc/config/arm/cortex-a57.md
@@ -297,7 +297,7 @@
        (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
 			alu_sreg,alus_sreg,logic_reg,logics_reg,\
 			adc_imm,adcs_imm,adc_reg,adcs_reg,\
-			adr,bfm,clz,csel,rbit,rev,alu_dsp_reg,\
+			adr,bfm,bfx,clz,rbit,rev,alu_dsp_reg,\
 			rotate_imm,shift_imm,shift_reg,\
 			mov_imm,mov_reg,\
 			mvn_imm,mvn_reg,\
diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md
index 318b151d64697001d0082295e54486a2ffcaa6e5..00574d7930f23c36005648cddca285405ced8a8c 100644
--- a/gcc/config/arm/exynos-m1.md
+++ b/gcc/config/arm/exynos-m1.md
@@ -358,7 +358,7 @@
 	    (eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\
 			     alu_sreg, alus_sreg, logic_reg, logics_reg,\
 			     adc_imm, adcs_imm, adc_reg, adcs_reg,\
-			     adr, bfm, clz, rbit, rev, csel, alu_dsp_reg,\
+			     adr, bfm, bfx, clz, rbit, rev, csel, alu_dsp_reg,\
 			     shift_imm, shift_reg, rotate_imm, extend,\
 			     mov_imm, mov_reg,\
 			     mvn_imm, mvn_reg,\
@@ -372,7 +372,7 @@
 	    (eq_attr "type" "alu_imm, alus_imm, logic_imm, logics_imm,\
 			     alu_sreg, alus_sreg, logic_reg, logics_reg,\
 			     adc_imm, adcs_imm, adc_reg, adcs_reg,\
-			     adr, bfm, clz, rbit, rev, alu_dsp_reg,\
+			     adr, bfm, bfx, clz, rbit, rev, alu_dsp_reg,\
 			     shift_imm, shift_reg, rotate_imm, extend,\
 			     mov_imm, mov_reg,\
 			     mvn_imm, mvn_reg,\
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 25f79b4d010ae24c14d97d9fead93db1eff42f32..7a95a3704d0907fcaf42463c5803cbff82b29fa1 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -51,6 +51,7 @@
 ; alus_shift_imm     as alu_shift_imm, setting condition flags.
 ; alus_shift_reg     as alu_shift_reg, setting condition flags.
 ; bfm                bitfield move operation.
+; bfx                bitfield extract operation.
 ; block              blockage insn, this blocks all functional units.
 ; branch             branch.
 ; call               subroutine call.
@@ -557,6 +558,7 @@
   alus_shift_imm,\
   alus_shift_reg,\
   bfm,\
+  bfx,\
   block,\
   branch,\
   call,\
diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md
index b7aeac6916353f9a02b56821e3df3c2f43fc2946..4f27b28461f23aff6720cd1ba54c46fa9ae574ce 100644
--- a/gcc/config/arm/xgene1.md
+++ b/gcc/config/arm/xgene1.md
@@ -164,7 +164,7 @@
 
 (define_insn_reservation "xgene1_bfm" 2
   (and (eq_attr "tune" "xgene1")
-       (eq_attr "type" "bfm"))
+       (eq_attr "type" "bfm,bfx"))
   "xgene1_decode1op,xgene1_fsu")
 
 (define_insn_reservation "xgene1_f_rint" 5

Follow-Ups:
- Re: [PATCH 1/2][AArch64] Add bfx attribute
  - From: Richard Earnshaw

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