Re: [PATCH] [ARC] Various small miscellaneous fixes.

[Andrew Burgess <andrew dot burgess at embecosm dot com>]

* Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com> [2016-11-01 16:28:34 +0100]:

> This is an updated version of the patch that can be applied as is.
> 
> Ok to apply?
> Claudiu
> 
> gcc/
> 2016-05-09  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.c (arc_process_double_reg_moves): Change.
> 	* config/arc/arc.md (movsi_insn): Disable unsupported move
> 	instructions for ARCv2 cores.
> 	(movdi): Use prepare_move_operands.
> 	(movsf, movdf): Use move_dest_operand predicate.
> 	(arc_process_double_reg_moves): Change.

arc_process_double_reg_moves line is duplicated, and "Change" seems a
little vague, even by GCC/ChangeLog standards.

> 	* config/arc/constraints.md (Chs): Enable when barrel shifter is
> 	present.
> 	* config/arc/fpu.md (divsf3): Change to divsf3_fpu.
> 	* config/arc/fpx.md (dexcl_3op_peep2_insn): Dx data register is
> 	also a destination.
> 	(dexcl_3op_peep2_insn_nores): Likewise.
> 	* config/arc/arc.h (SHIFT_COUNT_TRUNCATED): Define to one.
> 	(LINK_COMMAND_SPEC): Remove.

All the rest looks good.

Thanks,
Andrew






> ---
>  gcc/config/arc/arc.c          |  5 +----
>  gcc/config/arc/arc.h          | 27 +++------------------------
>  gcc/config/arc/arc.md         | 35 +++++++++++++++++++----------------
>  gcc/config/arc/constraints.md |  3 ++-
>  gcc/config/arc/fpu.md         |  6 ++++--
>  gcc/config/arc/fpx.md         | 26 ++++++++++++--------------
>  6 files changed, 41 insertions(+), 61 deletions(-)
> 
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index 0e7b63d..c927d5b 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -9021,10 +9021,7 @@ arc_process_double_reg_moves (rtx *operands)
>        rtx srcLow  = simplify_gen_subreg (SImode, src, DFmode,
>  					TARGET_BIG_ENDIAN ? 4 : 0);
>  
> -      emit_insn (gen_rtx_UNSPEC_VOLATILE (Pmode,
> -					  gen_rtvec (3, dest, srcHigh, srcLow),
> -					  VUNSPEC_ARC_DEXCL_NORES));
> -
> +      emit_insn (gen_dexcl_2op (dest, srcHigh, srcLow));
>      }
>    else
>      gcc_unreachable ();
> diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
> index b146f3a..17285a7 100644
> --- a/gcc/config/arc/arc.h
> +++ b/gcc/config/arc/arc.h
> @@ -128,24 +128,6 @@ along with GCC; see the file COPYING3.  If not see
>  		   %{!marclinux*: %{pg|p|profile:-marclinux_prof;: -marclinux}} \
>  		   %{!z:-z max-page-size=0x2000 -z common-page-size=0x2000} \
>  		   %{shared:-shared}"
> -/* Like the standard LINK_COMMAND_SPEC, but add %G when building
> -   a shared library with -nostdlib, so that the hidden functions of libgcc
> -   will be incorporated.
> -   N.B., we don't want a plain -lgcc, as this would lead to re-exporting
> -   non-hidden functions, so we have to consider libgcc_s.so.* first, which in
> -   turn should be wrapped with --as-needed.  */
> -#define LINK_COMMAND_SPEC "\
> -%{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\
> -    %(linker) %l " LINK_PIE_SPEC "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\
> -    %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\
> -    %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\
> -    %{fopenacc|fopenmp|%:gt(%{ftree-parallelize-loops=*:%*} 1):\
> -	%:include(libgomp.spec)%(link_gomp)}\
> -    %(mflib)\
> -    %{fprofile-arcs|fprofile-generate|coverage:-lgcov}\
> -    %{!nostdlib:%{!nodefaultlibs:%(link_ssp) %(link_gcc_c_sequence)}}\
> -    %{!A:%{!nostdlib:%{!nostartfiles:%E}}} %{T*} }}}}}}"
> -
>  #else
>  #define LINK_SPEC "%{mbig-endian:-EB} %{EB} %{EL}\
>    %{pg|p:-marcelf_prof;mA7|mARC700|mcpu=arc700|mcpu=ARC700: -marcelf}"
> @@ -1570,13 +1552,10 @@ extern int arc_return_address_regs[4];
>  /* Undo the effects of the movmem pattern presence on STORE_BY_PIECES_P .  */
>  #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3)
>  
> -/* Define this to be nonzero if shift instructions ignore all but the low-order
> -   few bits. Changed from 1 to 0 for rotate pattern testcases
> -   (e.g. 20020226-1.c). This change truncates the upper 27 bits of a word
> -   while rotating a word. Came to notice through a combine phase
> -   optimization viz. a << (32-b) is equivalent to a << (-b).
> +/* Define this to be nonzero if shift instructions ignore all but the
> +   low-order few bits.
>  */
> -#define SHIFT_COUNT_TRUNCATED 0
> +#define SHIFT_COUNT_TRUNCATED 1
>  
>  /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
>     is done just by pretending it is already truncated.  */
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index e127d5b..7147fbd 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -704,9 +704,9 @@
>  ; the iscompact attribute allows the epilogue expander to know for which
>  ; insns it should lengthen the return insn.
>  ; N.B. operand 1 of alternative 7 expands into pcl,symbol@gotpc .
> -(define_insn "*movsi_insn"                      ;   0     1     2    3  4 5   6   7   8   9   10  11  12    13   14  15  16     17     18 19   20    21    22 23 24    25 26  27   28   29
> -  [(set (match_operand:SI 0 "move_dest_operand" "=Rcq,Rcq#q,    w,   h, w,w,  w,  w,  w,  w,???w, ?w,  w,Rcq#q,   w,Rcq,  S,   Us<,RcqRck,!*x,  r,!*Rsd,!*Rcd,r,Ucm,  Usd,m,???m,VUsc,VUsc")
> -	(match_operand:SI 1 "move_src_operand"  "  cL,   cP,Rcq#q,hCm1,cL,I,Crr,Clo,Chi,Cbi,?Rac,Cpc,Clb, ?Cal,?Cal,  T,Rcq,RcqRck,   Us>,Usd,Ucm,  Usd,  Ucd,m,  w,!*Rzd,c,?Rac, Cm3, C32"))]
> +(define_insn "*movsi_insn"                      ;   0     1     2     3  4 5   6   7   8   9   10  11  12    13   14  15  16     17     18 19   20    21    22 23 24    25 26  27   28   29
> +  [(set (match_operand:SI 0 "move_dest_operand" "=Rcq,Rcq#q,    w,    h, w,w,  w,  w,  w,  w,???w, ?w,  w,Rcq#q,   w,Rcq,  S,   Us<,RcqRck,!*x,  r,!*Rsd,!*Rcd,r,Ucm,  Usd,m,???m,VUsc,VUsc")
> +	(match_operand:SI 1 "move_src_operand"  "  cL,   cP,Rcq#q,hPCm1,cL,I,Crr,Clo,Chi,Cbi,?Rac,Cpc,Clb, ?Cal,?Cal,  T,Rcq,RcqRck,   Us>,Usd,Ucm,  Usd,  Ucd,m,  w,!*Rzd,c,?Rac, Cm3, C32"))]
>    "register_operand (operands[0], SImode)
>     || register_operand (operands[1], SImode)
>     || (CONSTANT_P (operands[1])
> @@ -751,7 +751,7 @@
>     ; of Crr to 4.
>     (set_attr "length" "*,*,*,*,4,4,4,4,4,4,4,8,8,*,8,*,*,*,*,*,4,*,4,*,*,*,*,*,4,8")
>     (set_attr "predicable" "yes,no,yes,no,yes,no,no,no,no,no,yes,no,no,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no,no,no,no")
> -   (set_attr "cpu_facility" "*,*,av1,av2,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,av2,av2,*,*,av2,*,*,av2,*")])
> +   (set_attr "cpu_facility" "av1,av1,av1,av2,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,av2,av2,*,*,av2,*,*,av2,*")])
>  
>  ;; Sometimes generated by the epilogue code.  We don't want to
>  ;; recognize these addresses in general, because the limm is costly,
> @@ -1088,12 +1088,9 @@
>  	(match_operand:DI 1 "general_operand" ""))]
>    ""
>    "
> -{
> -  /* Everything except mem = const or mem = mem can be done easily.  */
> -
> -  if (GET_CODE (operands[0]) == MEM)
> -    operands[1] = force_reg (DImode, operands[1]);
> -}")
> +  if (prepare_move_operands (operands, DImode))
> +    DONE;
> +  ")
>  
>  (define_insn_and_split "*movdi_insn"
>    [(set (match_operand:DI 0 "move_dest_operand"      "=w, w,r,m")
> @@ -1140,7 +1137,7 @@
>  ;; Floating point move insns.
>  
>  (define_expand "movsf"
> -  [(set (match_operand:SF 0 "general_operand" "")
> +  [(set (match_operand:SF 0 "move_dest_operand" "")
>  	(match_operand:SF 1 "general_operand" ""))]
>    ""
>    "if (prepare_move_operands (operands, SFmode)) DONE;")
> @@ -1161,7 +1158,7 @@
>     (set_attr "iscompact" "true,false,false,false,false")])
>  
>  (define_expand "movdf"
> -  [(set (match_operand:DF 0 "nonimmediate_operand" "")
> +  [(set (match_operand:DF 0 "move_dest_operand" "")
>  	(match_operand:DF 1 "general_operand" ""))]
>    ""
>    "if (prepare_move_operands (operands, DFmode)) DONE;")
> @@ -1231,12 +1228,18 @@
>      ; second time to put back the contents which the first DEXCLx
>      ; will have overwritten
>      ; dexcl2 r0, r1, r0
> -    (set (match_dup 4) ; aka r0result
> -     	 ; aka DF, r1, r0
> -	 (unspec_volatile:SI [(match_dup 1) (match_dup 5) (match_dup 4)] VUNSPEC_ARC_DEXCL ))
> +    (parallel [
> +	       (set (match_dup 4) ; aka r0result
> +				  ; aka DF, r1, r0
> +		    (unspec_volatile:SI [(match_dup 5) (match_dup 4)]
> +					VUNSPEC_ARC_DEXCL))
> +	       (clobber (match_dup 1))
> +	       ])
>      ; Generate the second, which makes sure operand5 and operand4 values
>      ; are put back in the Dx register properly.
> -    (unspec_volatile:SI [(match_dup 1) (match_dup 5) (match_dup 4)] VUNSPEC_ARC_DEXCL_NORES )
> +    (set (match_dup 1) (unspec_volatile:DF
> +			[(match_dup 5) (match_dup 4)]
> +			VUNSPEC_ARC_DEXCL_NORES))
>  
>      ; Note: we cannot use a (clobber (match_scratch)) here because
>      ; the combine pass will end up replacing uses of it with 0
> diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md
> index b7bf2d3..8eccb2f 100644
> --- a/gcc/config/arc/constraints.md
> +++ b/gcc/config/arc/constraints.md
> @@ -256,7 +256,8 @@
>   "@internal
>    constant for a highpart that can be checked with a shift (asr.f 0,rn,m)"
>    (and (match_code "const_int")
> -       (match_test "IS_POWEROF2_P (-ival)")))
> +       (match_test "IS_POWEROF2_P (-ival)")
> +       (match_test "TARGET_BARREL_SHIFTER")))
>  
>  (define_constraint "Clo"
>   "@internal
> diff --git a/gcc/config/arc/fpu.md b/gcc/config/arc/fpu.md
> index 9b0a65d..e43047c 100644
> --- a/gcc/config/arc/fpu.md
> +++ b/gcc/config/arc/fpu.md
> @@ -193,11 +193,13 @@
>     (set_attr "type" "fpu")])
>  
>  ;; Division
> -(define_insn "divsf3"
> +(define_insn "*divsf3_fpu"
>    [(set (match_operand:SF 0 "register_operand"         "=r,r,r,r,r")
>  	(div:SF (match_operand:SF 1 "nonmemory_operand" "0,r,0,r,F")
>  		(match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))]
> -  "TARGET_FP_SP_SQRT"
> +  "TARGET_FP_SP_SQRT
> +   && (register_operand (operands[1], SFmode)
> +       || register_operand (operands[2], SFmode))"
>    "fsdiv%? %0,%1,%2"
>    [(set_attr "length" "4,4,8,8,8")
>     (set_attr "iscompact" "false")
> diff --git a/gcc/config/arc/fpx.md b/gcc/config/arc/fpx.md
> index 2e11157..9ed2b7c 100644
> --- a/gcc/config/arc/fpx.md
> +++ b/gcc/config/arc/fpx.md
> @@ -168,28 +168,26 @@
>  (set_attr "type" "lr")]
>  )
>  
> -
>  (define_insn "*dexcl_3op_peep2_insn"
>    [(set (match_operand:SI 0 "dest_reg_operand" "=r") ; not register_operand, to accept SUBREG
> -		   (unspec_volatile:SI [
> -		   			(match_operand:DF 1 "arc_double_register_operand" "D")
> -					(match_operand:SI 2 "shouldbe_register_operand" "r")  ; r1
> -					(match_operand:SI 3 "shouldbe_register_operand" "r") ; r0
> -					] VUNSPEC_ARC_DEXCL ))
> -  ]
> +	(unspec_volatile:SI
> +	 [(match_operand:SI 1 "shouldbe_register_operand" "r") ; r1
> +	  (match_operand:SI 2 "shouldbe_register_operand" "r") ; r0
> +	  ] VUNSPEC_ARC_DEXCL ))
> +   (clobber (match_operand:DF 3 "arc_double_register_operand" "=&D"))]
>    "TARGET_DPFP"
> -  "dexcl%F1 %0, %2, %3"
> +  "dexcl%F3 %0, %1, %2"
>    [(set_attr "type" "move")
>     (set_attr "length" "4")]
>  )
>  
>  ;; version which will not overwrite operand0
> -(define_insn "*dexcl_3op_peep2_insn_nores"
> -  [   (unspec_volatile:SI [
> -		   			(match_operand:DF 0 "arc_double_register_operand" "D")
> -					(match_operand:SI 1 "shouldbe_register_operand" "r")  ; r1
> -					(match_operand:SI 2 "shouldbe_register_operand" "r") ; r0
> -					] VUNSPEC_ARC_DEXCL_NORES )
> +(define_insn "dexcl_2op"
> +  [(set (match_operand:DF 0 "arc_double_register_operand" "=D")
> +	(unspec_volatile:DF
> +	 [(match_operand:SI 1 "shouldbe_register_operand" "r") ; r1
> +	  (match_operand:SI 2 "shouldbe_register_operand" "r") ; r0
> +	  ] VUNSPEC_ARC_DEXCL_NORES))
>    ]
>    "TARGET_DPFP"
>    "dexcl%F0 0, %1, %2"
> -- 
> 1.9.1
>