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Re: [PATCH], Allow SImode to go into VSX registers on PowerPC ISA 2.07 (power8) and above
- From: Segher Boessenkool <segher at kernel dot crashing dot org>
- To: Michael Meissner <meissner at linux dot vnet dot ibm dot com>, gcc-patches at gcc dot gnu dot org, David Edelsohn <dje dot gcc at gmail dot com>, Bill Schmidt <wschmidt at linux dot vnet dot ibm dot com>
- Date: Thu, 27 Oct 2016 14:55:51 -0500
- Subject: Re: [PATCH], Allow SImode to go into VSX registers on PowerPC ISA 2.07 (power8) and above
- Authentication-results: sourceware.org; auth=none
- References: <20161026225154.GA6588@ibm-tiger.the-meissners.org>
On Wed, Oct 26, 2016 at 06:51:54PM -0400, Michael Meissner wrote:
> (zero_extendsi<mode>2): Reorder pattern, so RLDICL comes before
> the FPR and VSX loads, but before MTVSRWZ. Remove ??, ! from the
> constraints. Add MFVSRWZ and XXEXTRACTUW instructions to support
> small integers in vector registers.
"but those before MTVSRWZ"? Or don't mention rldicl at all?
> (extendsi<mode>2): Reorder pattern, so EXTSW comes before the FPR
> and VSX loads, but before MTVSRWA. Remove ??, ! from the
> constraints. Add VEXTSW2D support for small integers in vector
> registers.
Similar here.
> @@ -3112,7 +3133,10 @@ rs6000_init_hard_regno_mode_ok (bool glo
> ww - Register class to do SF conversions in with VSX operations.
> wx - Float register if we can do 32-bit int stores.
> wy - Register class to do ISA 2.07 SF operations.
> - wz - Float register if we can do 32-bit unsigned int loads. */
> + wz - Float register if we can do 32-bit unsigned int loads.
> + wI - VSX register if SImode is allowed in VSX registers.
> + wJ - VSX register if QImode/HImode are allowed in VSX registers.
> + wK - Altivec register if QImode/HImode are allowed in VSX registers. */
You don't mention wH here, is that an oversight?
> /* Add support for various direct moves available. In this function, we only
> look at cases where we don't need any extra registers, and one or more
> - simple move insns are issued. At present, 32-bit integers are not allowed
> + simple move insns are issued. Originally small integers are not allowed
dot space space.
> @@ -5019,7 +5023,10 @@ (define_insn_and_split "floatsi<mode>2_l
> operands[1] = rs6000_address_for_fpconvert (operands[1]);
> if (GET_CODE (operands[2]) == SCRATCH)
> operands[2] = gen_reg_rtx (DImode);
> - emit_insn (gen_lfiwax (operands[2], operands[1]));
> + if (TARGET_VSX_SMALL_INTEGER)
> + emit_insn (gen_extendsidi2 (operands[2], operands[1]));
> + else
Trailing spaces here.
> + (match_operand:SI 1 "input_operand"
> + "r, U, m, Z, Z,
> + r, wI, wH, I, L,
> + n, wIwH, O, wM, wB,
Indent with tabs instead of spaces, like the other lines.
Everything looks fine except for those nits, and I'm really happy there
is no benchmark degradation :-)
Please install to trunk (if the -m32 and power7 runs work out fine).
Thanks,
Segher