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Hello! Attached patch fine-tunes the condition when prefetchw write prefetch insns are emitted. prefetchw is preferred for non-SSE2 K7 athlons (this is covered by i386-prefetch.exp tests), on the other hand, SSE prefetches are preferred for K8 targets, as measured and reported in PR 77270. For newer targets, PRFCHW cpuid bit is respected, and -march=native correctly emits prefetchw, when PRFCHW cpuid bit is set. (on a related note, PTA_PRFCHW should probably be set for amdfam10+ targets, Venkataramanan is looking into this issue). 2016-08-21 Uros Bizjak <ubizjak@gmail.com> PR target/77270 * config/i386/i386.md (prefetch): When TARGET_PRFCHW or TARGET_PREFETCHWT1 are disabled, emit 3dNOW! write prefetches for non-SSE2 athlons only, otherwise prefer SSE prefetches. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros.
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