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Re: [PATCH] Fix 4 avx512* mask reg constraints
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: Jakub Jelinek <jakub at redhat dot com>
- Cc: Kirill Yukhin <kirill dot yukhin at gmail dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Fri, 12 Aug 2016 16:05:49 +0200
- Subject: Re: [PATCH] Fix 4 avx512* mask reg constraints
- Authentication-results: sourceware.org; auth=none
- References: <20160812105119.GB14857@tucnak.redhat.com>
On Fri, Aug 12, 2016 at 12:51 PM, Jakub Jelinek <jakub@redhat.com> wrote:
> Hi!
>
> For the VEXTRACT* insns, I can't find anything that would make them
> special wrt. masking, so I believe they can't accept {%k0}, just
> no masking or {%k1} through {%k7}.
>
> I've tried to reproduce it with:
> #include <x86intrin.h>
>
> __m128i
> f1 (__m128i a, __m512i b, __mmask8 c)
> {
> register __mmask8 d __asm ("k0");
> d = c;
> asm ("" : "+k" (d));
> return _mm512_mask_extracti64x2_epi64 (a, d, b, 3);
> }
> but for some reason it still chose k1, still I believe k constraint
> is wrong in these cases.
>
> Ok for trunk?
>
> 2016-08-12 Jakub Jelinek <jakub@redhat.com>
>
> * config/i386/sse.md (avx512dq_vextract<shuffletype>64x2_1_maskm,
> vec_extract_hi_<mode>_mask, vec_extract_lo_<mode>_mask,
> vec_extract_hi_<mode>_mask): Use Yk constraint instead of k.
OK.
Thanks,
Uros.
> --- gcc/config/i386/sse.md.jj 2016-07-14 20:28:33.000000000 +0200
> +++ gcc/config/i386/sse.md 2016-08-12 12:14:19.618486123 +0200
> @@ -6957,7 +6957,7 @@ (define_insn "avx512dq_vextract<shufflet
> (parallel [(match_operand 2 "const_0_to_7_operand")
> (match_operand 3 "const_0_to_7_operand")]))
> (match_operand:<ssequartermode> 4 "memory_operand" "0")
> - (match_operand:QI 5 "register_operand" "k")))]
> + (match_operand:QI 5 "register_operand" "Yk")))]
> "TARGET_AVX512DQ
> && (INTVAL (operands[2]) % 2 == 0)
> && (INTVAL (operands[2]) == INTVAL (operands[3]) - 1)
> @@ -7171,7 +7171,7 @@ (define_insn "vec_extract_hi_<mode>_mask
> (const_int 12) (const_int 13)
> (const_int 14) (const_int 15)]))
> (match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
> - (match_operand:QI 3 "register_operand" "k")))]
> + (match_operand:QI 3 "register_operand" "Yk")))]
> "TARGET_AVX512DQ
> && rtx_equal_p (operands[2], operands[0])"
> "vextract<shuffletype>32x8\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}"
> @@ -7377,7 +7377,7 @@ (define_insn "vec_extract_lo_<mode>_mask
> (parallel [(const_int 0) (const_int 1)
> (const_int 2) (const_int 3)]))
> (match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
> - (match_operand:QI 3 "register_operand" "k")))]
> + (match_operand:QI 3 "register_operand" "Yk")))]
> "TARGET_AVX512VL && TARGET_AVX512F
> && rtx_equal_p (operands[2], operands[0])"
> "vextract<shuffletype>32x4\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}"
> @@ -7395,7 +7395,7 @@ (define_insn "vec_extract_hi_<mode>_mask
> (parallel [(const_int 4) (const_int 5)
> (const_int 6) (const_int 7)]))
> (match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
> - (match_operand:<ssehalfvecmode> 3 "register_operand" "k")))]
> + (match_operand:<ssehalfvecmode> 3 "register_operand" "Yk")))]
> "TARGET_AVX512F && TARGET_AVX512VL
> && rtx_equal_p (operands[2], operands[0])"
> "vextract<shuffletype>32x4\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}"
>
> Jakub