Re: [PATCH, 4 of 4], Enhance PowerPC vec_extract support for power8/power9 machines

[Michael Meissner <meissner at linux dot vnet dot ibm dot com>]

This is the 4th path to enhance vec_extract on 64-bit power8/power9 machines.

This patch uses the load from memory support and the variable elment patch that
were part of the previous patches for vector long/vector double, and adds the
same support for vector float, vector int, vector short, and vector char.

I have tested these patches with bootstrap builds and running make check on:

    1) Big endian power7 (both -m32 and -m64 tests done)
    2) Big endian power8 (only -m64 tests were done)
    3) Little endian power8

There were no regressions.  Can I check these patches into the trunk?

One further optimization would be to add support for constant element extracts
if the vector is currently in GPRs rather than vector registers on 64-bit
systems.  I'm not sure if it would be a win in general, or if it would cause
the register allocators to generate more moves between the GPR and vector
register banks.

[gcc]
2016-08-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
	Add support for vec_extract on vector float, vector int, vector
	short, and vector char vector types.
	* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add
	vector float, vector int, vector short, and vector char
	optimizations on 64-bit ISA 2.07 systems for both constant and
	variable element numbers.
	(rs6000_split_vec_extract_var): Likewise.
	* config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Allow SFmode to be
	Altivec registers on ISA 2.07 and above.
	(vsx_extract_v4sf): Delete alternative that hard coded element 0,
	which never was matched due to the split occuring before register
	allocation (and the code would not have worked on little endian
	systems if it did match).  Allow extracts to go to the Altivec
	registers if ISA 2.07 (power8).  Change from using "" around the
	C++ code to using {}'s.
	(vsx_extract_v4sf_<mode>_load): New insn to optimize vector float
	vec_extracts when the vector is in memory.
	(vsx_extract_v4sf_var): New insn to optimize vector float
	vec_extracts when the element number is variable on 64-bit ISA
	2.07 systems.
	(vsx_extract_<mode>, VSX_EXTRACT_I iterator): Add optimizations
	for 64-bit ISA 2.07 as well as ISA 3.0.
	(vsx_extract_<mode>_p9, VSX_EXTRACT_I iterator): Likewise.
	(vsx_extract_<mode>_p8, VSX_EXTRACT_I iterator): Likewise.
	(vsx_extract_<mode>_load, VSX_EXTRACT_I iterator): New insn to
	optimize vector int, vector short, and vector char vec_extracts
	when the vector is in memory.
	(vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): New insn to
	optimize vector int, vector short, and vector char vec_extracts
	when the element number is variable.

[gcc/testsuite]
2016-08-01  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/vec-extract-5.c: New tests to test
	vec_extract for vector float, vector int, vector short, and vector
	char.
	* gcc.target/powerpc/vec-extract-6.c: Likewise.
	* gcc.target/powerpc/vec-extract-7.c: Likewise.
	* gcc.target/powerpc/vec-extract-8.c: Likewise.
	* gcc.target/powerpc/vec-extract-9.c: Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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