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[Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequence
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: <gcc-patches at gcc dot gnu dot org>
- Cc: <nd at arm dot com>, <marcus dot shawcroft at arm dot com>, <richard dot earnshaw at arm dot com>
- Date: Tue, 17 May 2016 10:06:42 +0100
- Subject: [Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequence
- Authentication-results: sourceware.org; auth=none
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Hi,
This is just a simplification, it probably makes life easier for register
allocation in some corner cases and seems the right thing to do. We don't
use the internal version elsewhere, so we're safe to delete it and change
the types.
OK?
Bootstrapped on AArch64 with no issues.
Thanks,
James
---
2016-05-17 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_reduc_plus_internal<mode>): Rename to...
(reduc_plus_scal): ...This, and remove previous implementation.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index bd73bce..30023f0 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1989,19 +1989,6 @@
}
)
-(define_expand "reduc_plus_scal_<mode>"
- [(match_operand:<VEL> 0 "register_operand" "=w")
- (match_operand:V2F 1 "register_operand" "w")]
- "TARGET_SIMD"
- {
- rtx elt = GEN_INT (ENDIAN_LANE_N (<MODE>mode, 0));
- rtx scratch = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_aarch64_reduc_plus_internal<mode> (scratch, operands[1]));
- emit_insn (gen_aarch64_get_lane<mode> (operands[0], scratch, elt));
- DONE;
- }
-)
-
(define_insn "aarch64_reduc_plus_internal<mode>"
[(set (match_operand:VDQV 0 "register_operand" "=w")
(unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")]
@@ -2020,9 +2007,9 @@
[(set_attr "type" "neon_reduc_add")]
)
-(define_insn "aarch64_reduc_plus_internal<mode>"
- [(set (match_operand:V2F 0 "register_operand" "=w")
- (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")]
+(define_insn "reduc_plus_scal_<mode>"
+ [(set (match_operand:<VEL> 0 "register_operand" "=w")
+ (unspec:<VEL> [(match_operand:V2F 1 "register_operand" "w")]
UNSPEC_FADDV))]
"TARGET_SIMD"
"faddp\\t%<Vetype>0, %1.<Vtype>"