Re: [PATCH][PR rtl-optimization/69307] Handle hard registers in modes that span more than one register properly

[Andrey Belevantsev <abel at ispras dot ru>]

On 14.03.2016 21:39, Jeff Law wrote:
> On 03/14/2016 03:56 AM, Andrey Belevantsev wrote:
> > Thank you for checking this in.  I've also tested this patch in the
> > similar way (forcing selective scheduling for 2nd and both schedulers)
> > both on x86-64 and ia64.  I've posted the patches for remaining
> > sel-sched PRs just now -- it took some time bringing our Itaniums back
> > to life.
> No problem.  I found it trolling the P4/P5 regression list.  It was the
> only one that I could wrap my head around easily that night.

I forgot I had a test from BZ for this PR, it wasn't attached to the patch 
so it didn't get committed.  I've committed it now as rev. 234360.

Andrey

> Thanks for following-up on the others.  Hopefully between Alexander, Bernd
> and myself we can get them reviewed and work towards getting those BZs
> resolved.
>
> jeff

Index: gcc/testsuite/gcc.target/arm/pr69307.c
===================================================================
*** gcc/testsuite/gcc.target/arm/pr69307.c	(revision 0)
--- gcc/testsuite/gcc.target/arm/pr69307.c	(revision 234360)
***************
*** 0 ****
--- 1,34 ----
+ /* { dg-do run } */
+ /* { dg-options "-O2 -fselective-scheduling -mtune=arm1136j-s" } */
+ 
+ typedef unsigned char uint8_t;
+ typedef unsigned short int uint16_t;
+ typedef unsigned int uint32_t;
+ typedef unsigned long long int uint64_t;
+ typedef uint8_t u8;
+ typedef uint16_t u16;
+ typedef uint32_t u32;
+ typedef uint64_t u64;
+ u64 __attribute__((noinline, noclone))
+ foo(u8 u8_0, u16 u16_0, u32 u32_0, u64 u64_0, u8 u8_1, u16 u16_1, u32 u32_1, u64 u64_1, u8 u8_2, u16 u16_2, u32 u32_2, u64 u64_2, u8 u8_3, u16 u16_3, u32 u32_3, u64 u64_3)
+ {
+   u8 *p8_2 = &u8_2;
+   u16 *p16_2 = &u16_2;
+   u8 *p8_3 = &u8_3;
+   u64 *p64_3 = &u64_3;
+   p8_2 = &u8_3;
+   *p8_3 -= *p64_3;
+   *p8_2 = (u64)*p8_2 % ((u64)*p8_2 | 3);
+   u8_2 = (u64)u8_2 / ((u64)*p16_2 | 1);
+   u16_0 = (u64)u16_0 % ((u64)*p8_2 | 3);
+   return u8_0 + u16_0 + u32_0 + u64_0 + u8_1 + u16_1 + u32_1 + u64_1 + u8_2 + u16_2 + u32_2 + u64_2 + u8_3 + u16_3 + u32_3 + u64_3;
+ }
+ int main()
+ {
+   u64 x = 0;
+   x += foo(3llu, 6llu, 15llu, 28llu, 5llu, 11llu, 20llu, 44llu, 7llu, 10llu, 20llu, 55llu, 0llu, 9llu, 17llu, 48llu);
+   __builtin_printf("%02x%02x%02x%02x%02x%02x%02x%02x\n", (unsigned)((x >> 0) & 0xff), (unsigned)((x >> 8) & 0xff), (unsigned)((x >> 16) & 0xff), (unsigned)((x >> 24) & 0xff), (unsigned)((x >> 32) & 0xff), (unsigned)((x >> 40) & 0xff), (unsigned)((x >> 48) & 0xff), (unsigned)((x >> 56) & 0xff));
+   if (x != 0x1f3)
+     __builtin_abort();
+   return 0;
+ }
Index: gcc/testsuite/ChangeLog
===================================================================
*** gcc/testsuite/ChangeLog	(revision 234359)
--- gcc/testsuite/ChangeLog	(revision 234360)
***************
*** 1,5 ****
--- 1,10 ----
  2016-03-21  Andrey Belevantsev  <abel@ispras.ru>
  
+ 	PR rtl-optimization/69307
+ 	* gcc.target/arm/pr69307.c: New test.
+ 	
+ 2016-03-21  Andrey Belevantsev  <abel@ispras.ru>
+ 
  	PR rtl-optimization/69102
  	* gcc.c-torture/compile/pr69102.c: New test.