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[PATCH 04/10] gcc/arc: Replace rI constraint with r & Cm2 for ld and update insns

From: Andrew Burgess <andrew dot burgess at embecosm dot com>
To: gcc-patches at gcc dot gnu dot org
Cc: noamca at mellanox dot com, Claudiu dot Zissulescu at synopsys dot com, Andrew Burgess <andrew dot burgess at embecosm dot com>
Date: Fri, 4 Mar 2016 13:25:36 +0000
Subject: [PATCH 04/10] gcc/arc: Replace rI constraint with r & Cm2 for ld and update insns
Authentication-results: sourceware.org; auth=none
References: <cover dot 1457097757 dot git dot andrew dot burgess at embecosm dot com>
References: <cover dot 1457097757 dot git dot andrew dot burgess at embecosm dot com>

In the load*_update instructions the constraint 'rI' was being used,
which would accept either a register or a signed 12 bit constant.  The
problem is that the 32-bit form of ld with update only takes a signed
9-bit immediate.  As such, some ld instructions could be generated that
would, when assembled be 64-bit long, however, GCC believed them to be
32-bit long.  This error in the length would cause problems during
branch shortening.

The store*_update have the same restrictions on immediate size, however,
the patterns for these instructions already only accept 9-bit
immediates, and so should be safe.

gcc/ChangeLog:

	* config/arc/arc.md (*loadqi_update): Replace use of 'rI'
	constraint with separate 'r' and 'Cm2' constraints.
	(*load_zeroextendqisi_update): Likewise.
	(*load_signextendqisi_update): Likewise.
	(*loadhi_update): Likewise.
	(*load_zeroextendhisi_update): Likewise.
	(*load_signextendhisi_update): Likewise.
	(*loadsi_update): Likewise.
	(*loadsf_update): Likewise.
---
 gcc/ChangeLog.NPS400  | 12 +++++++
 gcc/config/arc/arc.md | 96 +++++++++++++++++++++++++--------------------------
 2 files changed, 60 insertions(+), 48 deletions(-)

diff --git a/gcc/ChangeLog.NPS400 b/gcc/ChangeLog.NPS400
index 716e413..71463df 100644
--- a/gcc/ChangeLog.NPS400
+++ b/gcc/ChangeLog.NPS400
@@ -1,3 +1,15 @@
+2016-02-01  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* config/arc/arc.md (*loadqi_update): Replace use of 'rI'
+	constraint with separate 'r' and 'Cm2' constraints.
+	(*load_zeroextendqisi_update): Likewise.
+	(*load_signextendqisi_update): Likewise.
+	(*loadhi_update): Likewise.
+	(*load_zeroextendhisi_update): Likewise.
+	(*load_signextendhisi_update): Likewise.
+	(*loadsi_update): Likewise.
+	(*loadsf_update): Likewise.
+
 2015-09-08  Andrew Burgess  <andrew.burgess@embecosm.com>
 	    Joern Rennecke  <joern.rennecke@embecosm.com>
 	    Noam Camus  <noamca@mellanox.com>
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 4193d26..99e8e30 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1151,40 +1151,40 @@
 
 ;; Note: loadqi_update has no 16-bit variant
 (define_insn "*loadqi_update"
-  [(set (match_operand:QI 3 "dest_reg_operand" "=r,r")
+  [(set (match_operand:QI 3 "dest_reg_operand" "=r,r,r")
         (match_operator:QI 4 "any_mem_operand"
-         [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-                   (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
-   (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+         [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+                   (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))]))
+   (set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "ldb.a%V4 %3,[%0,%S2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "4,8")])
+  [(set_attr "type" "load,load,load")
+   (set_attr "length" "4,4,8")])
 
 (define_insn "*load_zeroextendqisi_update"
-  [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
+  [(set (match_operand:SI 3 "dest_reg_operand" "=r,r,r")
 	(zero_extend:SI (match_operator:QI 4 "any_mem_operand"
-			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-			           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
-   (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+			           (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))])))
+   (set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "ldb.a%V4 %3,[%0,%S2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "4,8")])
+  [(set_attr "type" "load,load,load")
+   (set_attr "length" "4,4,8")])
 
 (define_insn "*load_signextendqisi_update"
-  [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
+  [(set (match_operand:SI 3 "dest_reg_operand" "=r,r,r")
 	(sign_extend:SI (match_operator:QI 4 "any_mem_operand"
-			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-			           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
-   (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+			           (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))])))
+   (set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "ldb.x.a%V4 %3,[%0,%S2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "4,8")])
+  [(set_attr "type" "load,load,load")
+   (set_attr "length" "4,4,8")])
 
 (define_insn "*storeqi_update"
   [(set (match_operator:QI 4 "any_mem_operand"
@@ -1201,41 +1201,41 @@
 ;; ??? pattern may have to be re-written
 ;; Note: no 16-bit variant for this pattern
 (define_insn "*loadhi_update"
-  [(set (match_operand:HI 3 "dest_reg_operand" "=r,r")
+  [(set (match_operand:HI 3 "dest_reg_operand" "=r,r,r")
 	(match_operator:HI 4 "any_mem_operand"
-	 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-	           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
-   (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
+	 [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+	           (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))]))
+   (set (match_operand:SI 0 "dest_reg_operand" "=w,w,w")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "ld%_.a%V4 %3,[%0,%S2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "4,8")])
+  [(set_attr "type" "load,load,load")
+   (set_attr "length" "4,4,8")])
 
 (define_insn "*load_zeroextendhisi_update"
-  [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
+  [(set (match_operand:SI 3 "dest_reg_operand" "=r,r,r")
 	(zero_extend:SI (match_operator:HI 4 "any_mem_operand"
-			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-			           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
-   (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+			           (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))])))
+   (set (match_operand:SI 0 "dest_reg_operand" "=r,r,r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "ld%_.a%V4 %3,[%0,%S2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "4,8")])
+  [(set_attr "type" "load,load,load")
+   (set_attr "length" "4,4,8")])
 
 ;; Note: no 16-bit variant for this instruction
 (define_insn "*load_signextendhisi_update"
-  [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
+  [(set (match_operand:SI 3 "dest_reg_operand" "=r,r,r")
 	(sign_extend:SI (match_operator:HI 4 "any_mem_operand"
-			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-			           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
-   (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
+			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+			           (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))])))
+   (set (match_operand:SI 0 "dest_reg_operand" "=w,w,w")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "ld%_.x.a%V4 %3,[%0,%S2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "4,8")])
+  [(set_attr "type" "load,load,load")
+   (set_attr "length" "4,4,8")])
 
 (define_insn "*storehi_update"
   [(set (match_operator:HI 4 "any_mem_operand"
@@ -1251,16 +1251,16 @@
 
 ;; No 16-bit variant for this instruction pattern
 (define_insn "*loadsi_update"
-  [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
+  [(set (match_operand:SI 3 "dest_reg_operand" "=r,r,r")
 	(match_operator:SI 4 "any_mem_operand"
-	 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-	           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
-   (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
+	 [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+	           (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))]))
+   (set (match_operand:SI 0 "dest_reg_operand" "=w,w,w")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "ld.a%V4 %3,[%0,%S2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "4,8")])
+  [(set_attr "type" "load,load,load")
+   (set_attr "length" "4,4,8")])
 
 (define_insn "*storesi_update"
   [(set (match_operator:SI 4 "any_mem_operand"
@@ -1275,16 +1275,16 @@
    (set_attr "length" "4")])
 
 (define_insn "*loadsf_update"
-  [(set (match_operand:SF 3 "dest_reg_operand" "=r,r")
+  [(set (match_operand:SF 3 "dest_reg_operand" "=r,r,r")
 	(match_operator:SF 4 "any_mem_operand"
-	 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-	           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
-   (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
+	 [(plus:SI (match_operand:SI 1 "register_operand" "0,0,0")
+	           (match_operand:SI 2 "nonmemory_operand" "r,Cm2,Cal"))]))
+   (set (match_operand:SI 0 "dest_reg_operand" "=w,w,w")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "ld.a%V4 %3,[%0,%S2]"
-  [(set_attr "type" "load,load")
-   (set_attr "length" "4,8")])
+  [(set_attr "type" "load,load,load")
+   (set_attr "length" "4,4,8")])
 
 (define_insn "*storesf_update"
   [(set (match_operator:SF 4 "any_mem_operand"
-- 
2.6.4

References:
- [PATCH 00/10] ARC: Add support for NPS400 variant
  - From: Andrew Burgess

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