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Re: [PATCH][AArch64] Replace insn to zero up DF register


On 03/01/16 13:02, Wilco Dijkstra wrote:
Evandro Menezes wrote:
The meaning of these attributes are not clear to me.  Is there a
reference somewhere about which insns are FP or SIMD or neither?
The meaning should be clear, "fp" is a floating point instruction, "simd" a SIMD one
as defined in ARM-ARM.

Indeed, I had to add the Y for the f_mcr insn to match it with nosimd.
However, I didn't feel that it should be moved to the right, since it's
already disparaged.  Am I missing something detail?
It might not matter for this specific case, but I have seen reload forcing the very
first alternative without looking at any costs or preferences - as long as it is legal.
This suggests we need to order alternatives from most preferred alternative to least
preferred one.

I think it is good enough for commit, James?

Methinks that my issue with those attributes is that I'm not as fluent in AArch64 as I'd like to be.

Please, feel free to edit the patch changing the order then.

Thank you,

--
Evandro Menezes


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