This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH] Fix memory alignment on AVX512VL masked floating point stores (PR target/69198)


On Fri, Jan 08, 2016 at 12:46:01PM -0800, H.J. Lu wrote:
> On Fri, Jan 8, 2016 at 12:44 PM, Jakub Jelinek <jakub@redhat.com> wrote:
> > On Fri, Jan 08, 2016 at 12:39:50PM -0800, H.J. Lu wrote:
> >> > p is not misaligned, it has just unknown alignment.
> >>
> >> And it may be 8 byte aligned.
> >
> > Yes.  But if you call the routine with just 8 byte aligned p,
> > you invoke undefined behavior.  So, there is nothing wrong on the testcase,
> > it tests what it means to.
> >
> 
> Testing what?  Undefined behavior?

No.  Testing that if you use an intrinsic through which you tell the
compiler the memory is aligned, it doesn't ignore that and actually uses
the instruction you've asked for.
If you use the *storeu* instrinsics instead, and if the compiler can't prove
the memory is sufficiently aligned, of course it has to use the unaligned
stores.

	Jakub


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]