Re: [PATCH][RTL-ifcvt] PR rtl-optimization/68841: Make sure one basic block doesn't clobber CC reg usage of the other

[Kyrill Tkachov <kyrylo dot tkachov at foss dot arm dot com>]

On 07/01/16 13:47, Bernd Schmidt wrote:
> On 01/07/2016 02:45 PM, Kyrill Tkachov wrote:
> > On 07/01/16 11:52, Bernd Schmidt wrote:
> > > I looked and this is indeed the case. Still slightly scary. Should the
> > > MEM be rtx_equal_p to TO_RENAME? It would be good to test or at least
> > > assert this.
> >
> > I tried asserting that and it caused trouble because a bit further up in
> > noce_process_if_block it does:
> >    /* Only operate on register destinations, and even then avoid extending
> >       the lifetime of hard registers on small register class machines.  */
> >    orig_x = x;
> >    if (!REG_P (x)
> >        || (HARD_REGISTER_P (x)
> >        && targetm.small_register_classes_for_mode_p (GET_MODE (x))))
> >      {
> >        if (GET_MODE (x) == BLKmode)
> >          return FALSE;
> >
> >        if (GET_CODE (x) == ZERO_EXTRACT
> >            && (!CONST_INT_P (XEXP (x, 1))
> >                || !CONST_INT_P (XEXP (x, 2))))
> >          return FALSE;
> >
> >        x = gen_reg_rtx (GET_MODE (GET_CODE (x) == STRICT_LOW_PART
> >                   ? XEXP (x, 0) : x));
> >      }
> >
> > It changes X to a register and after noce_try_cmove_arith it emits the
> > store.
>
> This suggests that orig_x needs to be passed to bbs_ok_for_cmove_arith, even disregarding the question of using it to assert that only expected MEMs are being modified.

Yes, which should be the original destinations of insn_a and insn_b of if_info.
I'll work on that. Though if we execute the above path then x will be a fresh new pseudo and so
will not cause any conflicts anyway.

Kyrill

> Bernd