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RE: [PATCH][AArch64] Avoid emitting zero immediate as zero register
- From: Wilco Dijkstra <Wilco dot Dijkstra at arm dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: nd <nd at arm dot com>
- Date: Tue, 15 Dec 2015 11:17:35 +0000
- Subject: RE: [PATCH][AArch64] Avoid emitting zero immediate as zero register
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ping
> -----Original Message-----
> From: Wilco Dijkstra [mailto:wdijkstr@arm.com]
> Sent: 28 October 2015 17:33
> To: GCC Patches
> Subject: [PATCH][AArch64] Avoid emitting zero immediate as zero register
>
> Several instructions accidentally emit wzr/xzr even when the pattern specifies an immediate. Fix this by removing the register
> specifier in patterns that emit immediates.
>
> Passes regression tests. OK for commit?
>
> ChangeLog:
> 2015-10-28 Wilco Dijkstra <wdijkstr@arm.com>
>
> * gcc/config/aarch64/aarch64.md (ccmp_and<mode>): Emit
> immediate as %1.
> (ccmp_ior<mode>): Likewise.
> (add<mode>3_compare0): Likewise.
> (addsi3_compare0_uxtw): Likewise.
> (add<mode>3nr_compare0): Likewise.
> (compare_neg<mode>): Likewise.
> (<optab><mode>3): Likewise.
>
> ---
> gcc/config/aarch64/aarch64.md | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index f90b821..d262102 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -275,7 +275,7 @@
> "aarch64_ccmp_mode_to_code (GET_MODE (operands[1])) == GET_CODE (operands[5])"
> "@
> ccmp\\t%<w>2, %<w>3, %k5, %m4
> - ccmp\\t%<w>2, %<w>3, %k5, %m4
> + ccmp\\t%<w>2, %3, %k5, %m4
> ccmn\\t%<w>2, %n3, %k5, %m4"
> [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
> )
> @@ -294,7 +294,7 @@
> "aarch64_ccmp_mode_to_code (GET_MODE (operands[1])) == GET_CODE (operands[5])"
> "@
> ccmp\\t%<w>2, %<w>3, %K5, %M4
> - ccmp\\t%<w>2, %<w>3, %K5, %M4
> + ccmp\\t%<w>2, %3, %K5, %M4
> ccmn\\t%<w>2, %n3, %K5, %M4"
> [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
> )
> @@ -1647,7 +1647,7 @@
> ""
> "@
> adds\\t%<w>0, %<w>1, %<w>2
> - adds\\t%<w>0, %<w>1, %<w>2
> + adds\\t%<w>0, %<w>1, %2
> subs\\t%<w>0, %<w>1, %n2"
> [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
> )
> @@ -1664,7 +1664,7 @@
> ""
> "@
> adds\\t%w0, %w1, %w2
> - adds\\t%w0, %w1, %w2
> + adds\\t%w0, %w1, %2
> subs\\t%w0, %w1, %n2"
> [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
> )
> @@ -1846,7 +1846,7 @@
> ""
> "@
> cmn\\t%<w>0, %<w>1
> - cmn\\t%<w>0, %<w>1
> + cmn\\t%<w>0, %1
> cmp\\t%<w>0, %n1"
> [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
> )
> @@ -2792,7 +2792,7 @@
> ""
> "@
> cmp\\t%<w>0, %<w>1
> - cmp\\t%<w>0, %<w>1
> + cmp\\t%<w>0, %1
> cmn\\t%<w>0, %n1"
> [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
> )
> @@ -3178,7 +3178,7 @@
> ""
> "@
> <logical>\\t%<w>0, %<w>1, %<w>2
> - <logical>\\t%<w>0, %<w>1, %<w>2
> + <logical>\\t%<w>0, %<w>1, %2
> <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
> [(set_attr "type" "logic_reg,logic_imm,neon_logic")
> (set_attr "simd" "*,*,yes")]
> --
> 1.9.1