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Re: [AArch64][dejagnu][PATCH 5/7] Dejagnu support for ARMv8.1 Adv.SIMD.
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- Cc: Bernhard Reutner-Fischer <rep dot dot dot nop at gmail dot com>, gcc-patches at gcc dot gnu dot org
- Date: Wed, 25 Nov 2015 10:56:29 +0000
- Subject: Re: [AArch64][dejagnu][PATCH 5/7] Dejagnu support for ARMv8.1 Adv.SIMD.
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- References: <562A2519 dot 3020102 at foss dot arm dot com> <562A26FA dot 6070601 at foss dot arm dot com> <F7DFA4BA-5D63-4C20-9B85-C1423E4CBBC8 at gmail dot com> <562F98F4 dot 7050606 at foss dot arm dot com> <20151123122419 dot GA11516 at arm dot com> <565340ED dot 7080700 at foss dot arm dot com> <56558929 dot 4030204 at foss dot arm dot com>
On Wed, Nov 25, 2015 at 10:10:49AM +0000, Matthew Wahab wrote:
> On 23/11/15 16:38, Matthew Wahab wrote:
> >On 23/11/15 12:24, James Greenhalgh wrote:
> >>On Tue, Oct 27, 2015 at 03:32:04PM +0000, Matthew Wahab wrote:
> >>>On 24/10/15 08:16, Bernhard Reutner-Fischer wrote:
> >>>>On October 23, 2015 2:24:26 PM GMT+02:00, Matthew Wahab
> >>>><matthew.wahab@foss.arm.com> wrote:
> >>>>>The ARMv8.1 architecture extension adds two Adv.SIMD instructions,.
> >>>>>This
> >>>>>patch adds support in Dejagnu for ARMv8.1 Adv.SIMD specifiers and
> >>>>>checks.
> >>>>>
> >>>>>The new test options are
> >>>>>- { dg-add-options arm_v8_1a_neon }: Add compiler options needed to
> >>>>> enable ARMv8.1 Adv.SIMD.
> >>>>>- { dg-require-effective-target arm_v8_1a_neon_hw }: Require a target
> >>>>> capable of executing ARMv8.1 Adv.SIMD instructions.
> >>>>>
>
> >>>+# Return 1 if the target supports executing the ARMv8.1 Adv.SIMD extension, 0
> >>>+# otherwise. The test is valid for AArch64.
> >>>+
> >>>+proc check_effective_target_arm_v8_1a_neon_hw { } {
> >>>+ if { ![check_effective_target_arm_v8_1a_neon_ok] } {
> >>>+ return 0;
> >>>+ }
> >>>+ return [check_runtime_nocache arm_v8_1a_neon_hw_available {
> >>>+ int
> >>>+ main (void)
> >>>+ {
> >>>+ long long a = 0, b = 1;
> >>>+ long long result = 0;
> >>>+
> >>>+ asm ("sqrdmlah %s0,%s1,%s2"
> >>>+ : "=w"(result)
> >>>+ : "w"(a), "w"(b)
> >>>+ : /* No clobbers. */);
> >>
> >>Hm, those types look wrong, I guess this works but it is an unusual way
> >>to write it. I presume this is to avoid including arm_neon.h each time, but
> >>you could just directly use the internal type names for the arm_neon types.
> >>That is to say __Int32x4_t (or whichever mode you intend to use).
> >>
> >
> >I'll rework the patch to use the internal types names.
>
> Attached, the reworked patch which uses internal type __Int32x2_t and
> cleans up the assembler.
>
> Retested aarch64-none-elf with cross-compiled check-gcc on an ARMv8.1
> emulator. Also re-ran the cross-compiled
> gcc.target/aarch64/advsimd-intrinsics tests for aarch64-none-elf on an
> ARMv8 emulator.
OK.
Thanks,
James
> gcc/testsuite
> 2015-11-24 Matthew Wahab <matthew.wahab@arm.com>
>
> * lib/target-supports.exp (add_options_for_arm_v8_1a_neon): New.
> (check_effective_target_arm_arch_FUNC_ok)
> (add_options_for_arm_arch_FUNC)
> (check_effective_target_arm_arch_FUNC_multilib): Add "armv8.1-a"
> to the list to be generated.
> (check_effective_target_arm_v8_1a_neon_ok_nocache): New.
> (check_effective_target_arm_v8_1a_neon_ok): New.
> (check_effective_target_arm_v8_1a_neon_hw): New.