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Re: [PATCH AArch64]Handle REG+REG+CONST and REG+NON_REG+CONST in legitimize address
- From: Jiong Wang <jiong dot wang at foss dot arm dot com>
- To: Richard Earnshaw <Richard dot Earnshaw at foss dot arm dot com>, "Bin.Cheng" <amker dot cheng at gmail dot com>
- Cc: James Greenhalgh <james dot greenhalgh at arm dot com>, Bin Cheng <bin dot cheng at arm dot com>, gcc-patches List <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 24 Nov 2015 13:06:27 +0000
- Subject: Re: [PATCH AArch64]Handle REG+REG+CONST and REG+NON_REG+CONST in legitimize address
- Authentication-results: sourceware.org; auth=none
- References: <000001d12119$49548570$dbfd9050$ at arm dot com> <20151117100800 dot GA6727 at arm dot com> <CAHFci2_fK2LFS8cjaePZr66tCgL8YufmrswyYUGUFb00MbTMRQ at mail dot gmail dot com> <CAHFci28V+bXsQecQyju2oHcVJ0iM1RKcn6c8jandB-jpk9ufgA at mail dot gmail dot com> <564F5ABF dot 2020302 at foss dot arm dot com> <CAHFci2-SyJsy4UJK2_Z9p9Xztc=5yurHChsAYBc=b8R3sqT5uw at mail dot gmail dot com> <5654343A dot 2080609 at foss dot arm dot com> <56543963 dot 3070704 at foss dot arm dot com>
On 24/11/15 10:18, Richard Earnshaw wrote:
I presume you are aware of the canonicalization rules for add? That is,
for a shift-and-add operation, the shift operand must appear first. Ie.
(plus (shift (op, op)), op)
not
(plus (op, (shift (op, op))
R.
Looks to me it's not optimal to generate invalid mem addr, for example
(mem (plus reg, (mult reg, imm))) or even the simple (mem (plus (plus r,
r), imm),
in the first place. Those complex rtx inside is hidden by the permissive
memory_operand predication, and only exposed during reload by stricter
constraints, then reload need to extra work. If we expose those complex rtx
earlier then some earlier rtl pass may find more optimization
opportunities, for
example combine.
The following simple modification fix the ICE and generates best
sequences to me:
- return gen_rtx_fmt_ee (PLUS, addr_mode, base, op1);
+ addr = gen_rtx_fmt_ee (PLUS, addr_mode, op1, base);
+ emit_insn (gen_rtx_SET (base, addr));
+ return base;
67 add x1, x29, 48
68 add x1, x1, x0, sxtw 3
69 stlr x19, [x1]
instead of
67 add x1, x29, 64
68 add x0, x1, x0, sxtw 3
69 sub x0, x0, #16
70 stlr x19, [x0]
or
67 sxtw x0, w0
68 add x1, x29, 48
69 add x1, x1, x0, sxtw 3
70 stlr x19, [x1]