Re: [PATCH 1/2] simplify-rtx: Simplify trunc of and of shiftrt

[Uros Bizjak <ubizjak at gmail dot com>]

On Fri, Nov 13, 2015 at 3:36 PM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> Hi!
>
> On Fri, Nov 13, 2015 at 11:02:55AM +0100, Uros Bizjak wrote:
>> on alpha-linux-gnu.
>>
>> The difference starts in combine, where before the patch, we were able
>> to combine insns:
>>
>> (insn 7 6 8 2 (set (reg:DI 82)
>>         (lshiftrt:DI (reg:DI 81 [ x ])
>>             (const_int 16 [0x10]))) pr42269-1.c:8 66 {lshrdi3}
>>      (expr_list:REG_DEAD (reg:DI 81 [ x ])
>>         (nil)))
>> (insn 8 7 11 2 (set (reg:DI 70 [ _2 ])
>>         (sign_extend:DI (subreg:SI (reg:DI 82) 0))) pr42269-1.c:8 2
>> {*extendsidi2_1}
>>      (expr_list:REG_DEAD (reg:DI 82)
>>         (nil)))
>>
>> to:
>>
>> Trying 7 -> 8:
>> Successfully matched this instruction:
>> (set (reg:DI 70 [ _2 ])
>>     (zero_extract:DI (reg/v:DI 80 [ x ])
>>         (const_int 16 [0x10])
>>         (const_int 16 [0x10])))
>> allowing combination of insns 7 and 8
>> original costs 4 + 4 = 8
>> replacement cost 4
>> deferring deletion of insn with uid = 7.
>> modifying insn i3     8: r70:DI=zero_extract(r80:DI,0x10,0x10)
>> deferring rescan insn with uid = 8.
>>
>> After the patch, the combination fails:
>>
>> Trying 7 -> 8:
>> Failed to match this instruction:
>> (set (reg:DI 70 [ _2 ])
>>     (sign_extend:DI (lshiftrt:SI (subreg:SI (reg/v:DI 80 [ x ]) 0)
>>             (const_int 16 [0x10]))))
>
> Somehow, before the patch, it decided to do a zero-extension (where the
> combined insns had a sign extension).  Was that even correct?  Maybe
> many bits of reg 80 (or, hrm, 81 in the orig?!) are known zero?

Oops, this analysis is wrong. I'll re-do the analysis in reported PR 68330 [1].

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68330

Uros.