Re: [PATCH][ARM]Fix addsi3_compare_op2 pattern.

[Kyrill Tkachov <kyrylo dot tkachov at arm dot com>]

Hi Renlin,

On 12/11/15 09:29, Renlin Li wrote:
> Hi all,
>
> This is a simply patch to adjust the assembly output for addsi3_compare_op2 rtx pattern in ARM backend.
>
> According to the constraints, it's the second alternative which allows the second operand to be a constant.
> The original pattern will trigger an ICE when the third alternative is chosen, and trying to output a constant while the second operand is a register.
>
> This is triggered by my experimental backend changes. branch 5, 4.9 all have this problem.
>
> arm-none-linux-gnueabihf bootstrap Okay, arm-none-eabi regression test Okay.
>
> Okay to commit into trunk and backport to branch 5 and 4.9?
>
> Regards,
> Renlin Li
>
> gcc/ChangeLog:
>
> 2015-11-12  Renlin Li  <renlin.li@arm.com>
>
>     * config/arm/arm.md (addsi3_compare_op2): Make the order of
>         assembly pattern consistent with constraint order.

Yes, this is ok. I think the order of the alternatives is obviously wrong.

For context, this is the whole pattern:
(define_insn "*addsi3_compare_op2"
  [(set (reg:CC_C CC_REGNUM)
    (compare:CC_C
     (plus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
          (match_operand:SI 2 "arm_add_operand" "I,L,r"))
     (match_dup 2)))
   (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
    (plus:SI (match_dup 1) (match_dup 2)))]
  "TARGET_32BIT"
  "@
   add%.\\t%0, %1, %2
   add%.\\t%0, %1, %2
   sub%.\\t%0, %1, #%n2"
  [(set_attr "conds" "set")
   (set_attr "type" "alus_imm,alus_imm,alus_sreg")]
)

Thanks,
Kyrill