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Re: [Patch ARM] Switch ARM to unified asm.


Hi Ramana,

On 11/10/2015 12:48 PM, Ramana Radhakrishnan wrote:
[Resending as I managed to muck this up with my mail client]

Hi,

I held off committing a previous version of this patch that I posted in July to be nice to folks backporting fixes and to watch for any objections to move the ARM backend completely over into the unified assembler.

The patch does the following.

* The compiler now generates code in all ISA modes in unified asm.
* We've had unified asm only for the last 10 years, ever since the first Thumb2 support was put in, the disassembler generates output in unified assembler, while the compiler output is always in divided syntax for ARM state.
* This means patterns get simpler not having to worry about the position of the condition in a conditional instruction. For example we now consistently use
    a. ldrbeq rather than ldreqb
    b. movseq rather than moveqs
    c. Or indeed the appropriate push / pop instructions whereever appropriate.


The compiler behaviour has not changed in terms of what it does with inline assembler, that still remains in divided syntax and over time we need to move all of this over to unified syntax if we can do so as all the official documentation is now in terms of unified asm. I've been carrying this in my tree for quite a while and am reasonably happy that it is stable. I will watch out for any fallout in the coming weeks with this but it is better to take this now rather than later given we are hitting the end of stage1.

Tested on arm-none-eabi - applied to trunk.



I see a failure with an outdated check for the unified assembly. OK to fix ?



2015-11-06  Christian Bruel  <christian.bruel@st.com>

	* gcc.target/arm/mmx-1.c: Adjust for unified asm.

Index: gcc.target/arm/mmx-1.c
===================================================================
--- gcc.target/arm/mmx-1.c	(revision 230111)
+++ gcc.target/arm/mmx-1.c	(working copy)
@@ -8,7 +8,7 @@
 /* { dg-options "-O -mno-apcs-frame -mcpu=iwmmxt -mabi=iwmmxt" } */
 /* { dg-require-effective-target arm32 } */
 /* { dg-require-effective-target arm_iwmmxt_ok } */
-/* { dg-final { scan-assembler "ldmfd\[ 	]sp!.*ip,\[ ]*pc" } } */
+/* { dg-final { scan-assembler "push.*ip,\[ ]*pc" } } */
 
 /* This function uses all the call-saved registers, namely r4, r5, r6,
    r7, r8, r9, sl, fp.  Since we also save lr, that leaves an odd

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