[PATCH][AArch64][12/14] Target attributes and target pragmas tests

[Kyrill Tkachov <kyrylo dot tkachov at arm dot com>]

Hi all,

These are the tests for target attributes and pragmas.
I've tried to test for the inlining rules, some of the possible errors and the preprocessor macros changed from target pragmas.

Ok for trunk?

Thanks,
Kyrill

2015-07-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    * gcc.target/aarch64/pragma-cpp-predefs-1.c: New test.
    * gcc.target/aarch64/target-attr-1.c: Likewise.
    * gcc.target/aarch64/target-attr-2.c: Likewise.
    * gcc.target/aarch64/target-attr-3.c: Likewise.
    * gcc.target/aarch64/target-attr-4.c: Likewise.
    * gcc.target/aarch64/target-attr-5.c: Likewise.
    * gcc.target/aarch64/target-attr-6.c: Likewise.
    * gcc.target/aarch64/target-attr-7.c: Likewise.
    * gcc.target/aarch64/target-attr-8.c: Likewise.
    * gcc.target/aarch64/target-attr-9.c: Likewise.
    * gcc.target/aarch64/target-attr-10.c: Likewise.
    * gcc.target/aarch64/target-attr-11.c: Likewise.
    * gcc.target/aarch64/target-attr-12.c: Likewise.
    * gcc.target/aarch64/target-attr-13.c: Likewise.
    * gcc.target/aarch64/target-attr-14.c: Likewise.

commit 1218b6fe4dd6d3429793d62369a878047a9f9a35
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Thu May 21 15:21:44 2015 +0100

    [AArch64][12/N] Target attributes and target pragmas tests

diff --git a/gcc/testsuite/gcc.target/aarch64/pragma-cpp-predefs-1.c b/gcc/testsuite/gcc.target/aarch64/pragma-cpp-predefs-1.c
new file mode 100644
index 0000000..779220e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pragma-cpp-predefs-1.c
@@ -0,0 +1,255 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8-a+crypto" } */
+
+/* Test  that pragma option pushing and popping works.
+   Also that CPP predefines redefinitions on #pragma works.  */
+
+#pragma GCC push_options
+#pragma GCC target("arch=armv8-a+nofp+nosimd")
+#ifdef __ARM_FEATURE_FMA
+#error "__ARM_FEATURE_FMA defined but shouldn't!"
+#endif
+
+#ifdef __ARM_FP
+#error "__ARM_FP defined but shouldn't!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("arch=armv8-a+fp+nosimd")
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON defined but shouldn't!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("arch=armv8-a+fp+simd")
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON not defined but should!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO defined but shouldn't!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("arch=armv8-a+fp+simd+crypto")
+
+#ifndef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO not defined but should!"
+#endif
+
+#pragma GCC pop_options
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON not defined but should!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO defined but shouldn't!"
+#endif
+
+
+#pragma GCC pop_options
+
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON defined but shouldn't!"
+#endif
+
+#pragma GCC pop_options
+
+#ifdef __ARM_FP
+#error "__ARM_FP is defined but shouldn't!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON defined but shouldn't!"
+#endif
+
+/* And again, but using cpu=.  */
+
+#pragma GCC push_options
+#pragma GCC target("cpu=cortex-a53+nofp+nosimd")
+#ifdef __ARM_FEATURE_FMA
+#error "__ARM_FEATURE_FMA defined but shouldn't!"
+#endif
+
+#ifdef __ARM_FP
+#error "__ARM_FP defined but shouldn't!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("cpu=cortex-a53+fp+nosimd")
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON defined but shouldn't!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("cpu=cortex-a53+fp+simd+nocrypto")
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON not defined but should!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO defined but shouldn't!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("cpu=cortex-a53+fp+simd+crypto")
+
+#ifndef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO not defined but should!"
+#endif
+
+
+#pragma GCC pop_options
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON not defined but should!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO defined but shouldn't!"
+#endif
+
+
+#pragma GCC pop_options
+
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON defined but shouldn't!"
+#endif
+
+#pragma GCC pop_options
+
+#ifdef __ARM_FP
+#error "__ARM_FP is defined but shouldn't!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON defined but shouldn't!"
+#endif
+
+/* And again, but using just the isa extensions.  */
+
+#pragma GCC push_options
+#pragma GCC target("+nofp")
+#ifdef __ARM_FEATURE_FMA
+#error "__ARM_FEATURE_FMA defined but shouldn't!"
+#endif
+
+#ifdef __ARM_FP
+#error "__ARM_FP defined but shouldn't!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("+fp+nosimd")
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON defined but shouldn't!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("+fp+simd+nocrypto")
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON not defined but should!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO defined but shouldn't!"
+#endif
+
+#pragma GCC push_options
+#pragma GCC target("+fp+simd+crypto")
+
+#ifndef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO not defined but should!"
+#endif
+
+#pragma GCC pop_options
+
+#ifndef __ARM_NEON
+#error "__ARM_NEON not defined but should!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO defined but shouldn't!"
+#endif
+
+
+#pragma GCC pop_options
+
+#ifndef __ARM_FP
+#error "__ARM_FP is not defined but should!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON defined but shouldn't!"
+#endif
+
+#pragma GCC pop_options
+
+#ifdef __ARM_FP
+#error "__ARM_FP is defined but shouldn't!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON defined but shouldn't!"
+#endif
+
+/* Make sure that general-regs-only works too.  */
+#pragma GCC push_options
+#pragma GCC target("general-regs-only")
+#ifdef __ARM_FEATURE_FMA
+#error "__ARM_FEATURE_FMA defined but shouldn't!"
+#endif
+
+#ifdef __ARM_FP
+#error "__ARM_FP defined but shouldn't!"
+#endif
+
+#ifdef __ARM_NEON
+#error "__ARM_NEON defined but shouldn't!"
+#endif
+
+#ifdef __ARM_FEATURE_CRYPTO
+#error "__ARM_FEATURE_CRYPTO defined but shouldn't!"
+#endif
+
+#pragma GCC pop_options
+
+/* Also check that crc re-defines work.  */
+#pragma GCC target("+nocrc")
+#ifdef __ARM_FEATURE_CRC32
+#error "__ARM_FEATURE_CRC32 defined but shouldn't!"
+#endif
+
+#pragma GCC target("+crc")
+#ifndef __ARM_FEATURE_CRC32
+#error "__ARM_FEATURE_CRC32 not defined but should!"
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-1.c b/gcc/testsuite/gcc.target/aarch64/target-attr-1.c
new file mode 100644
index 0000000..94c934c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=thunderx -save-temps" } */
+
+__attribute__((target("cpu=cortex-a72.cortex-a53")))
+int
+foo (int a)
+{
+  return a + 1;
+}
+
+/* { dg-final { scan-assembler "//.tune cortex-a72.cortex-a53" } } */
+/* { dg-final { scan-assembler-not "thunderx" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-10.c b/gcc/testsuite/gcc.target/aarch64/target-attr-10.c
new file mode 100644
index 0000000..a33b930
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-10.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8-a+simd" } */
+
+/* Using a SIMD intrinsic from a function tagged with nosimd should fail
+   due to inlining rules.  */
+
+#include "arm_neon.h"
+
+__attribute__((target("+nosimd")))
+uint8x16_t
+foo (uint8x16_t a, uint8x16_t b, uint8x16_t c)
+{
+  return vbslq_u8 (a, b, c); /* { dg-error "called from here" } */
+}
+
+/* { dg-error "inlining failed in call to always_inline" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-11.c b/gcc/testsuite/gcc.target/aarch64/target-attr-11.c
new file mode 100644
index 0000000..f248b35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-11.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+
+__attribute__((target("no-general-regs-only")))
+int
+foo (int a)
+{
+  return a + 1;
+}
+
+/* { dg-error "does not allow a negated form" "" { target *-*-* } 0 } */
+/* { dg-error "is invalid" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-12.c b/gcc/testsuite/gcc.target/aarch64/target-attr-12.c
new file mode 100644
index 0000000..18af5b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-12.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+
+__attribute__((target("general-regs-only=+crc")))
+int
+foo (int a)
+{
+  return a + 1;
+}
+
+/* { dg-error "does not accept an argument" "" { target *-*-* } 0 } */
+/* { dg-error "is invalid" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-13.c b/gcc/testsuite/gcc.target/aarch64/target-attr-13.c
new file mode 100644
index 0000000..2c9e935
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-13.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8-a+crc+crypto" } */
+
+#include "arm_acle.h"
+
+__attribute__((target("+crc+nocrypto")))
+int
+foo (uint32_t a, uint8_t b)
+{
+  return __crc32b (a, b);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-14.c b/gcc/testsuite/gcc.target/aarch64/target-attr-14.c
new file mode 100644
index 0000000..fea61fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-14.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Inlining non-strict-align functions into strict-align
+   functions is allowed.  */
+
+int
+bar (int a)
+{
+  return a - 6;
+}
+
+__attribute__((target("strict-align")))
+int
+bam (int a)
+{
+  return a - bar (a);
+}
+
+/* { dg-final { scan-assembler-not "bl.*bar" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-2.c b/gcc/testsuite/gcc.target/aarch64/target-attr-2.c
new file mode 100644
index 0000000..a4f32ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=cortex-a57 -ftree-vectorize -fdump-tree-vect-all" } */
+
+__attribute__((target("+nosimd")))
+int
+baz (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] += 5;
+}
+
+__attribute__((target("arch=armv8-a+nosimd")))
+int
+baz2 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] += 5;
+}
+
+__attribute__((target("cpu=cortex-a53+nosimd")))
+int
+baz3 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] += 5;
+}
+
+__attribute__((target("general-regs-only")))
+int
+baz4 (int *a)
+{
+  for (int i = 0; i < 1024; i++)
+    a[i] += 5;
+}
+
+/* { dg-final { scan-tree-dump-not "vectorized 1 loops" "vect" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-3.c b/gcc/testsuite/gcc.target/aarch64/target-attr-3.c
new file mode 100644
index 0000000..be5e2c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-3.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-fix-cortex-a53-835769 -save-temps" } */
+
+/* Check that the attribute overrides the command line option
+   and the fix is applied once.  */
+
+__attribute__((target("fix-cortex-a53-835769")))
+unsigned long
+test (unsigned long a, double b, unsigned long c, unsigned long d, unsigned long *e)
+{
+  double result;
+  volatile unsigned long tmp = *e;
+  __asm__ __volatile ("// %0, %1"
+                      : "=w" (result)
+                      : "0" (b)
+                      :    /* No clobbers */
+                      );
+  return c * d + d;
+}
+
+unsigned long
+test2 (unsigned long a, double b, unsigned long c, unsigned long d, unsigned long *e)
+{
+  double result;
+  volatile unsigned long tmp = *e;
+  __asm__ __volatile ("// %0, %1"
+                      : "=w" (result)
+                      : "0" (b)
+                      :    /* No clobbers */
+                      );
+  return c * d + d;
+}
+
+/* { dg-final { scan-assembler-times "between mem op and" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-4.c b/gcc/testsuite/gcc.target/aarch64/target-attr-4.c
new file mode 100644
index 0000000..f2d9bc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-4.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8-a+nocrc -save-temps" } */
+
+#include "arm_acle.h"
+
+__attribute__((target("+crc")))
+uint32_t
+foo (uint32_t a, uint8_t b)
+{
+  return __crc32b (a, b);
+}
+
+__attribute__((target("arch=armv8-a+crc")))
+uint32_t
+fooarch (uint32_t a, uint8_t b)
+{
+  return __crc32b (a, b);
+}
+
+__attribute__((target("cpu=cortex-a53+crc")))
+uint32_t
+foocpu (uint32_t a, uint8_t b)
+{
+  return __crc32b (a, b);
+}
+
+
+/* { dg-final { scan-assembler-times "crc32b\tw..?, w..?, w..?\n" 3 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-5.c b/gcc/testsuite/gcc.target/aarch64/target-attr-5.c
new file mode 100644
index 0000000..809334d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-5.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Make sure that bar is inlined into bam.  */
+
+__attribute__((target("arch=armv8-a+nocrc")))
+int
+bar (int a)
+{
+  return a - 6;
+}
+
+__attribute__((target("cpu=cortex-a53+nocrc")))
+int
+bam (int a)
+{
+  return a - bar (a);
+}
+
+/* { dg-final { scan-assembler-not "bl.*bar" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-6.c b/gcc/testsuite/gcc.target/aarch64/target-attr-6.c
new file mode 100644
index 0000000..eff1210
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-6.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* Inlining strict-align functions into non-strict align
+   functions is not allowed.  */
+
+__attribute__((target("strict-align")))
+int
+bar (int a)
+{
+  return a - 6;
+}
+
+int
+bam (int a)
+{
+  return a - bar (a);
+}
+
+/* { dg-final { scan-assembler "bl.*bar" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-7.c b/gcc/testsuite/gcc.target/aarch64/target-attr-7.c
new file mode 100644
index 0000000..5967d08
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-7.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mcpu=thunderx -save-temps" } */
+
+/* Make sure that #pragma overrides command line option and
+   target attribute overrides the pragma.  */
+
+#pragma GCC target("cpu=xgene1")
+
+int
+bar (int a)
+{
+  return a - 6;
+}
+
+__attribute__((target("tune=cortex-a53")))
+int
+bam (int a)
+{
+  return a - bar (a);
+}
+
+/* { dg-final { scan-assembler-times "//.tune xgene1" 1 } } */
+/* { dg-final { scan-assembler-times "//.tune cortex-a53" 1 } } */
+/* { dg-final { scan-assembler-not "thunderx" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-8.c b/gcc/testsuite/gcc.target/aarch64/target-attr-8.c
new file mode 100644
index 0000000..1cb0778
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-8.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* bar has a subset arch of bam.  Inlining should be allowed.  */
+
+__attribute__((target("arch=armv8-a+nocrc")))
+int
+bar (int a)
+{
+  return a - 6;
+}
+
+__attribute__((target("arch=armv8-a+crc")))
+int
+bam (int a)
+{
+  return a - bar (a);
+}
+
+
+/* { dg-final { scan-assembler-not "bl.*bar" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/target-attr-9.c b/gcc/testsuite/gcc.target/aarch64/target-attr-9.c
new file mode 100644
index 0000000..44bd809
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/target-attr-9.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -save-temps" } */
+
+/* bar is not a subset arch of bam.  Inlining should be rejected.  */
+
+__attribute__((target("arch=armv8-a+crc")))
+int
+bar (int a)
+{
+  return a - 6;
+}
+
+__attribute__((target("arch=armv8-a+nocrc")))
+int
+bam (int a)
+{
+  return a - bar (a);
+}
+
+
+/* { dg-final { scan-assembler "bl.*bar" } } */