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[patch committed SH] Fix PR target/66410
- From: Kaz Kojima <kkojima at rr dot iij4u dot or dot jp>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sat, 06 Jun 2015 08:44:16 +0900 (JST)
- Subject: [patch committed SH] Fix PR target/66410
- Authentication-results: sourceware.org; auth=none
The attached patch is to fix PR target/66410 which is an ICE in
lra-assigns.c:assign_by_spills with -mlra.
The insn *mov[qh]i has Snd/r alternative which is problematic
when Snd is memory with index addressing and r is reloading with
r0 because only r0 can become the index register on this target.
The patch disparages this case for RA. It fixes PR and various
libstdc++ test failures happen on trunk with -mlra. Tested on
sh4-unknown-linux-gnu with no new failures. Committed.
Regards,
kaz
--
2015-06-05 Kaz Kojima <kkojima@gcc.gnu.org>
PR target/66410
* config/sh/constraints.md (Sid, Ssd): New memory constraints.
* config/sh/sh.md (*mov<mode>): Use Sid and Ssd alternatives
instead of Snd. Disparage Sid/z alternative with '^'.
diff --git a/config/sh/constraints.md b/config/sh/constraints.md
index bd059a4..4d1eb2d 100644
--- a/config/sh/constraints.md
+++ b/config/sh/constraints.md
@@ -309,6 +309,19 @@
(and (match_code "mem")
(match_test "! satisfies_constraint_Sdd (op)")))
+(define_memory_constraint "Sid"
+ "A memory reference that uses index addressing."
+ (and (match_code "mem")
+ (match_code "plus" "0")
+ (match_code "reg" "00")
+ (match_code "reg" "01")))
+
+(define_memory_constraint "Ssd"
+ "A memory reference that excludes index and displacement addressing."
+ (and (match_code "mem")
+ (match_test "! satisfies_constraint_Sid (op)")
+ (match_test "! satisfies_constraint_Sdd (op)")))
+
(define_memory_constraint "Sbv"
"A memory reference, as used in SH2A bclr.b, bset.b, etc."
(and (match_test "MEM_P (op) && GET_MODE (op) == QImode")
diff --git a/config/sh/sh.md b/config/sh/sh.md
index 634a612..2d10ddb 100644
--- a/config/sh/sh.md
+++ b/config/sh/sh.md
@@ -7430,18 +7430,18 @@ label:
;; Q/r has to come first, otherwise PC relative loads might wrongly get
;; placed into delay slots. Since there is no QImode PC relative load, the
;; Q constraint and general_movsrc_operand will reject it for QImode.
-;; The Snd alternatives should come before Sdd in order to avoid a preference
-;; of using r0 als the register operand for addressing modes other than
-;; displacement addressing.
+;; The Sid/Ssd alternatives should come before Sdd in order to avoid
+;; a preference of using r0 als the register operand for addressing modes
+;; other than displacement addressing. Sid/z is disparaged by '^'.
;; The Sdd alternatives allow only r0 as register operand, even though on
;; SH2A any register could be allowed by switching to a 32 bit insn.
;; Generally sticking to the r0 is preferrable, since it generates smaller
;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
(define_insn "*mov<mode>"
[(set (match_operand:QIHI 0 "general_movdst_operand"
- "=r,r,r,Snd,r, Sdd,z, r,l")
+ "=r,r,r,Sid,^zr,Ssd,r, Sdd,z, r,l")
(match_operand:QIHI 1 "general_movsrc_operand"
- "Q,r,i,r, Snd,z, Sdd,l,r"))]
+ "Q,r,i,^zr,Sid,r, Ssd,z, Sdd,l,r"))]
"TARGET_SH1
&& (arith_reg_operand (operands[0], <MODE>mode)
|| arith_reg_operand (operands[1], <MODE>mode))"
@@ -7453,9 +7453,11 @@ label:
mov.<bw> %1,%0
mov.<bw> %1,%0
mov.<bw> %1,%0
+ mov.<bw> %1,%0
+ mov.<bw> %1,%0
sts %1,%0
lds %1,%0"
- [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset")
+ [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset")
(set (attr "length")
(cond [(and (match_operand 0 "displacement_mem_operand")
(not (match_operand 0 "short_displacement_mem_operand")))