[PATCH][AARCH64]Use shl for vec_shr_<mode> rtx pattern.

[Renlin Li <renlin dot li at arm dot com>]

Hi all,

unsigned shift left dosen't support immediate shift. Previouly, gcc will 
generate asm instruction like this: "ushl d1, d0, 32", which is not a 
legal insn and will be rejected by assembler. This patch change the use 
of ushl in vec_shr_<mode> into shl.

A test case is added, and it passes on both aarch64-none-elf and 
aarch64_be-none-elf tool-chain.

Okay to commit?

Regards,
Renlin Li

gcc/ChangeLog:

2015-04-28  Renlin Li  <renlin.li@arm.com>

    * config/aarch64/aarch64-simd.md (vec_shr_<mode>): Use shl.

gcc/testsuite/ChangeLog:

2015-04-28  Renlin Li  <renlin.li@arm.com>
                    Alan Lawrence  <alan.lawrence@arm.com>

    * gcc.target/aarch64/vect-reduc-or_1.c: New.

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 0557570..41706fb 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -788,7 +788,7 @@
   "TARGET_SIMD"
   {
     if (BYTES_BIG_ENDIAN)
-      return "ushl %d0, %d1, %2";
+      return "shl %d0, %d1, %2";
     else
       return "ushr %d0, %d1, %2";
   }
diff --git a/gcc/testsuite/gcc.target/aarch64/vect-reduc-or_1.c b/gcc/testsuite/gcc.target/aarch64/vect-reduc-or_1.c
new file mode 100644
index 0000000..f5d9460
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vect-reduc-or_1.c
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-all" } */
+/* Write a reduction loop to be reduced using whole vector right shift.  */
+
+extern void abort(void);
+
+unsigned char in[8] __attribute__((__aligned__(16)));
+
+int
+main (unsigned char argc, char **argv)
+{
+  unsigned char i = 0;
+  unsigned char sum = 1;
+
+  for (i = 0; i < 8; i++)
+    in[i] = (i + i + 1) & 0xfd;
+
+  /* Prevent constant propagation of the entire loop below.  */
+  asm volatile ("" : : : "memory");
+
+  for (i = 0; i < 8; i++)
+    sum |= in[i];
+
+  if (sum != 13)
+    {
+      __builtin_printf("Failed %d\n", sum);
+      abort();
+    }
+
+  return 0;
+}
+
+/* { dg-final { scan-tree-dump "Reduce using vector shifts" "vect" } } */
+/* { dg-final { cleanup-tree-dump "vect" } } */