This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH, rs6000, testsuite, PR65456] Changes for unaligned vector load/store support on POWER8
- From: "Bin.Cheng" <amker dot cheng at gmail dot com>
- To: Bill Schmidt <wschmidt at linux dot vnet dot ibm dot com>
- Cc: gcc-patches List <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 27 Apr 2015 14:23:15 +0800
- Subject: Re: [PATCH, rs6000, testsuite, PR65456] Changes for unaligned vector load/store support on POWER8
- Authentication-results: sourceware.org; auth=none
- References: <1427650979 dot 2939 dot 33 dot camel at gnopaine>
On Mon, Mar 30, 2015 at 1:42 AM, Bill Schmidt
<wschmidt@linux.vnet.ibm.com> wrote:
> Hi,
>
> This is a follow-up to
> https://gcc.gnu.org/ml/gcc-patches/2015-03/msg00103.html, which adds
> support for faster unaligned vector memory accesses on POWER8. As
> pointed out in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65456, there
> was a piece missing here. The target macro SLOW_UNALIGNED_ACCESS is
> still evaluating to 1 for unaligned vector accesses on POWER8, which
> causes some scalarization to occur during expand. This version of the
> patch fixes this as well.
>
> The only changes from before are the update to config/rs6000/rs6000.h,
> and the new test case gcc.target/powerpc/pr65456.c. Is this ok for
> trunk after 5 branches, and backports to 4.8, 4.9, 5 thereafter?
>
> Thanks,
> Bill
>
>
> [gcc]
>
> 2015-03-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
>
> * config/rs6000/rs6000.c (rs6000_option_override_internal): For
> VSX + POWER8, enable TARGET_ALLOW_MOVMISALIGN and
> TARGET_EFFICIENT_UNALIGNED_VSX if not selected by command line
> option. However, for -mno-allow-movmisalign, be sure to disable
> TARGET_EFFICIENT_UNALIGNED_VSX to avoid an ICE.
> (rs6000_builtin_mask_for_load): Return 0 for targets with
> efficient unaligned VSX accesses so that the vectorizer will use
> direct unaligned loads.
> (rs6000_builtin_support_vector_misalignment): Always return true
> for targets with efficient unaligned VSX accesses.
> (rs6000_builtin_vectorization_cost): Cost of unaligned loads and
> stores on targets with efficient unaligned VSX accesses is almost
> always the same as the cost of an aligned load or store, so model
> it that way.
> * config/rs6000/rs6000.h (SLOW_UNALIGNED_ACCESS): Evaluate to
> zero for unaligned vector accesses on POWER8.
> * config/rs6000/rs6000.opt (mefficient-unaligned-vector): New
> undocumented option.
>
> [gcc/testsuite]
>
> 2015-03-29 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
>
> * gcc.dg/vect/bb-slp-24.c: Exclude test for POWER8.
> * gcc.dg/vect/bb-slp-25.c: Likewise.
> * gcc.dg/vect/bb-slp-29.c: Likewise.
> * gcc.dg/vect/bb-slp-32.c: Replace vect_no_align with
> vect_no_align && { ! vect_hw_misalign }.
> * gcc.dg/vect/bb-slp-9.c: Likewise.
> * gcc.dg/vect/costmodel/ppc/costmodel-slp-33.c: Exclude test for
> vect_hw_misalign.
> * gcc.dg/vect/costmodel/ppc/costmodel-vect-31a.c: Likewise.
> * gcc.dg/vect/costmodel/ppc/costmodel-vect-76b.c: Adjust tests to
> account for POWER8, where peeling for alignment is not needed.
> * gcc.dg/vect/costmodel/ppc/costmodel-vect-outer-fir.c: Replace
> vect_no_align with vect_no_align && { ! vect_hw_misalign }.
> * gcc.dg.vect.if-cvt-stores-vect-ifcvt-18.c: Likewise.
> * gcc.dg/vect/no-scevccp-outer-6-global.c: Likewise.
> * gcc.dg/vect/no-scevccp-outer-6.c: Likewise.
> * gcc.dg/vect/no-vfa-vect-43.c: Likewise.
> * gcc.dg/vect/no-vfa-vect-57.c: Likewise.
> * gcc.dg/vect/no-vfa-vect-61.c: Likewise.
> * gcc.dg/vect/no-vfa-vect-depend-1.c: Likewise.
> * gcc.dg/vect/no-vfa-vect-depend-2.c: Likewise.
> * gcc.dg/vect/no-vfa-vect-depend-3.c: Likewise.
> * gcc.dg/vect/pr16105.c: Likewise.
> * gcc.dg/vect/pr20122.c: Likewise.
> * gcc.dg/vect/pr33804.c: Likewise.
> * gcc.dg/vect/pr33953.c: Likewise.
> * gcc.dg/vect/pr56787.c: Likewise.
> * gcc.dg/vect/pr58508.c: Likewise.
> * gcc.dg/vect/slp-25.c: Likewise.
> * gcc.dg/vect/vect-105-bit-array.c: Likewise.
> * gcc.dg/vect/vect-105.c: Likewise.
> * gcc.dg/vect/vect-27.c: Likewise.
> * gcc.dg/vect/vect-29.c: Likewise.
> * gcc.dg/vect/vect-33.c: Exclude unaligned access test for
> POWER8.
> * gcc.dg/vect/vect-42.c: Replace vect_no_align with vect_no_align
> && { ! vect_hw_misalign }.
> * gcc.dg/vect/vect-44.c: Likewise.
> * gcc.dg/vect/vect-48.c: Likewise.
> * gcc.dg/vect/vect-50.c: Likewise.
> * gcc.dg/vect/vect-52.c: Likewise.
> * gcc.dg/vect/vect-56.c: Likewise.
> * gcc.dg/vect/vect-60.c: Likewise.
> * gcc.dg/vect/vect-72.c: Likewise.
> * gcc.dg/vect/vect-75-big-array.c: Likewise.
> * gcc.dg/vect/vect-75.c: Likewise.
> * gcc.dg/vect/vect-77-alignchecks.c: Likewise.
> * gcc.dg/vect/vect-77-global.c: Likewise.
> * gcc.dg/vect/vect-78-alignchecks.c: Likewise.
> * gcc.dg/vect/vect-78-global.c: Likewise.
> * gcc.dg/vect/vect-93.c: Likewise.
> * gcc.dg/vect/vect-95.c: Likewise.
> * gcc.dg/vect/vect-96.c: Likewise.
> * gcc.dg/vect/vect-cond-1.c: Likewise.
> * gcc.dg/vect/vect-cond-3.c: Likewise.
> * gcc.dg/vect/vect-cond-4.c: Likewise.
> * gcc.dg/vect/vect-cselim-1.c: Likewise.
> * gcc.dg/vect/vect-multitypes-1.c: Likewise.
> * gcc.dg/vect/vect-multitypes-3.c: Likewise.
> * gcc.dg/vect/vect-multitypes-4.c: Likewise.
> * gcc.dg/vect/vect-multitypes-6.c: Likewise.
> * gcc.dg/vect/vect-nest-cycle-1.c: Likewise.
> * gcc.dg/vect/vect-nest-cycle-2.c: Likewise.
> * gcc.dg/vect/vect-outer-3a-big-array.c: Likewise.
> * gcc.dg/vect/vect-outer-3a.c: Likewise.
> * gcc.dg/vect/vect-outer-5.c: Likewise.
> * gcc.dg/vect/vect-outer-fir-big-array.c: Likewise.
> * gcc.dg/vect/vect-outer-fir-lb-big-array.c: Likewise.
> * gcc.dg/vect/vect-outer-fir-lb.c: Likewise.
> * gcc.dg/vect/vect-outer-fir.c: Likewise.
> * gcc.dg/vect/vect-peel-3.c: Likewise.
> * gcc.dg/vect/vect-peel-4.c: Likewise.
> * gcc.dg/vect/vect-pre-interact.c: Likewise.
> * gcc.target/powerpc/pr65456.c: New test.
> * gcc.target/powerpc/vsx-vectorize-2.c: Exclude test for POWER8.
> * gcc.target/powerpc/vsx-vectorize-4.c: Likewise.
> * gcc.target/powerpc/vsx-vectorize-6.c: Likewise.
> * gcc.target/powerpc/vsx-vectorize-7.c: Likewise.
> * gfortran.dg/vect/vect-2.f90: Replace vect_no_align with
> vect_no_align && { ! vect_hw_misalign }.
> * gfortran.dg/vect/vect-3.f90: Likewise.
> * gfortran.dg/vect/vect-4.f90: Likewise.
> * gfortran.dg/vect/vect-5.f90: Likewise.
> * lib/target-supports.exp (check_effective_target_vect_no_align):
> Return 1 for POWER8.
> (check_effective_target_vect_hw_misalign): Return 1 for POWER8.
> (check_vect_support_and_set_flags): Don't set
> -mno-allow-movmisalign for POWER8 vector hardware.
>
>
> Index: gcc/testsuite/gcc.dg/vect/vect-33.c
> ===================================================================
> --- gcc/testsuite/gcc.dg/vect/vect-33.c (revision 221118)
> +++ gcc/testsuite/gcc.dg/vect/vect-33.c (working copy)
> @@ -36,9 +36,10 @@ int main (void)
> return main1 ();
> }
>
> +/* vect_hw_misalign && { ! vect64 } */
>
> /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
> -/* { dg-final { scan-tree-dump "Vectorizing an unaligned access" "vect" { target { vect_hw_misalign && { {! vect64} || vect_multiple_sizes } } } } } */
> +/* { dg-final { scan-tree-dump "Vectorizing an unaligned access" "vect" { target { { { ! powerpc*-*-* } && vect_hw_misalign } && { { ! vect64 } || vect_multiple_sizes } } } } } */
> /* { dg-final { scan-tree-dump "Alignment of access forced using peeling" "vect" { target { vector_alignment_reachable && { vect64 && {! vect_multiple_sizes} } } } } } */
> /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { { {! vector_alignment_reachable} || {! vect64} } && {! vect_hw_misalign} } } } } */
> /* { dg-final { cleanup-tree-dump "vect" } } */
Hi Bill,
With this change, the test case is skipped on aarch64 now. Since it
passed before, Is it expected to act like this on 64bit platforms?
PASS->NA: gcc.dg/vect/vect-33.c -flto -ffat-lto-objects
scan-tree-dump-times vect "Vectorizing an unaligned access" 0
PASS->NA: gcc.dg/vect/vect-33.c scan-tree-dump-times vect "Vectorizing
an unaligned access" 0
Thanks,
bin