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Re: [AArch64][PR65139] use clobber with match_scratch for aarch64_lshr_sisd_or_int_<mode>3
- From: Richard Earnshaw <Richard dot Earnshaw at foss dot arm dot com>
- To: Kugan <kugan dot vivekanandarajah at linaro dot org>, Jakub Jelinek <jakub at redhat dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, James Greenhalgh <James dot Greenhalgh at arm dot com>, Maxim Kuvyrkov <maxim dot kuvyrkov at linaro dot org>
- Date: Sat, 18 Apr 2015 15:07:16 +0100
- Subject: Re: [AArch64][PR65139] use clobber with match_scratch for aarch64_lshr_sisd_or_int_<mode>3
- Authentication-results: sourceware.org; auth=none
- References: <552D897C dot 2040207 at linaro dot org> <552E571C dot 3000306 at foss dot arm dot com> <20150415123202 dot GW1725 at tucnak dot redhat dot com> <552EE5CC dot 9040703 at linaro dot org> <20150415223248 dot GZ1725 at tucnak dot redhat dot com> <552EED9F dot 3060901 at linaro dot org>
On 16/04/15 00:00, Kugan wrote:
>
>
> On 16/04/15 08:32, Jakub Jelinek wrote:
>> On Thu, Apr 16, 2015 at 08:27:24AM +1000, Kugan wrote:
>>> + if (<CODE> == LSHIFTRT)
>>> + {
>>> + emit_insn (gen_aarch64_lshr_sisd_or_int_<mode>3 (operands[0], operands[1], operands[2]));
>>
>> That is way too long line, please wrap it.
>>
>>> + DONE;
>>> + }
>>> }
>>> )
>>>
>>> @@ -3361,11 +3367,12 @@
>>> )
>>>
>>> ;; Logical right shift using SISD or Integer instruction
>>> -(define_insn "*aarch64_lshr_sisd_or_int_<mode>3"
>>> - [(set (match_operand:GPI 0 "register_operand" "=w,&w,r")
>>> +(define_insn "aarch64_lshr_sisd_or_int_<mode>3"
>>> + [(set (match_operand:GPI 0 "register_operand" "=w,w,r")
>>> (lshiftrt:GPI
>>> (match_operand:GPI 1 "register_operand" "w,w,r")
>>> - (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,w,rUs<cmode>")))]
>>> + (match_operand:QI 2 "aarch64_reg_or_shift_imm_<mode>" "Us<cmode>,w,rUs<cmode>")))
>>
>> Though, this one too...
>>
>
> Fixed in the attached patch.
>
> Thanks,
> Kugan
>
Not ok.
You need to ensure that your scratch register cannot overlap op1, since
the scratch is written before op1 is read.
R.