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RFA: RL78:
- From: Nick Clifton <nickc at redhat dot com>
- To: dj at redhat dot com
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Tue, 14 Apr 2015 17:53:43 +0100
- Subject: RFA: RL78:
- Authentication-results: sourceware.org; auth=none
Hi DJ,
I would like permission to apply this patch to the RL78 backend. It
tidies up a few minor bugs, specifically:
* The prologue instruction to increment the stack pointer by a large
amount was not being marked as frame related.
* The %p operand operator was not using %code when applied to a
function symbol.
* Reload could in very rare circumstances fail to compute a suitable
register class.
* The expanders in rl78.md contain constraints that are not used.
* The multiply insns in rl78.md mark operand 1 as both input and
output when in fact it is only an input.
Tested with no regressions on an rl78-elf toolchain.
OK to apply ?
Cheers
Nick
2015-04-14 Nick Clifton <nickc@redhat.com>
* config/rl78/rl78.c (rl78_expand_prologue): Mark large stack
decrement instruction as being frame related.
(rl78_print_operand_1): Handle 'p' modifier to add +0 to HL
based addresses.
If zero extending a function address enclose the operation in
%code(...).
(rl78_preferred_reload_class): New function.
(TARGET_PREFERRED_RELOAD_CLASS): Define.
* config/rl78/rl78.md: Remove useless constraints in expanders.
(mulqi3_rl78): Remove + qualifier on input-only operand 1.
(mulhi3_rl78): Likewise.
(mulhi3_g13): Likewise.
(mulsi3_rl78): Likewise.
(es_addr): Move to before the multiply patterns.
Index: config/rl78/rl78.c
===================================================================
--- config/rl78/rl78.c (revision 222096)
+++ config/rl78/rl78.c (working copy)
@@ -1322,7 +1322,7 @@
emit_move_insn (ax, sp);
emit_insn (gen_subhi3 (ax, ax, GEN_INT (fs)));
- insn = emit_move_insn (sp, ax);
+ insn = F (emit_move_insn (sp, ax));
add_reg_note (insn, REG_FRAME_RELATED_EXPR,
gen_rtx_SET (SImode, sp,
gen_rtx_PLUS (HImode, sp, GEN_INT (-fs))));
@@ -1570,6 +1570,7 @@
e - third QI of an SI (i.e. where the ES register gets values from)
E - fourth QI of an SI (i.e. MSB)
+ p - Add +0 to a zero-indexed HL based address.
*/
/* Implements the bulk of rl78_print_operand, below. We do it this
@@ -1644,13 +1645,16 @@
rl78_print_operand_1 (file, XEXP (XEXP (op, 0), 1), 'u');
fprintf (file, "[");
rl78_print_operand_1 (file, XEXP (XEXP (op, 0), 0), 0);
+ if (letter == 'p' && GET_CODE (XEXP (op, 0)) == REG)
+ fprintf (file, "+0");
fprintf (file, "]");
}
else
{
+ op = XEXP (op, 0);
fprintf (file, "[");
- rl78_print_operand_1 (file, XEXP (op, 0), letter);
- if (letter == 'p' && GET_CODE (XEXP (op, 0)) == REG)
+ rl78_print_operand_1 (file, op, letter);
+ if (letter == 'p' && REG_P (op) && REGNO (op) == 6)
fprintf (file, "+0");
fprintf (file, "]");
}
@@ -1772,15 +1776,41 @@
if (GET_CODE (XEXP (op, 0)) == ZERO_EXTEND)
{
- rl78_print_operand_1 (file, XEXP (op, 1), letter);
- fprintf (file, "+");
- rl78_print_operand_1 (file, XEXP (op, 0), letter);
+ if (GET_CODE (XEXP (op, 1)) == SYMBOL_REF
+ && SYMBOL_REF_DECL (XEXP (op, 1))
+ && TREE_CODE (SYMBOL_REF_DECL (XEXP (op, 1))) == FUNCTION_DECL)
+ {
+ fprintf (file, "%%code(");
+ assemble_name (file, rl78_strip_nonasm_name_encoding (XSTR (XEXP (op, 1), 0)));
+ fprintf (file, "+");
+ rl78_print_operand_1 (file, XEXP (op, 0), letter);
+ fprintf (file, ")");
+ }
+ else
+ {
+ rl78_print_operand_1 (file, XEXP (op, 1), letter);
+ fprintf (file, "+");
+ rl78_print_operand_1 (file, XEXP (op, 0), letter);
+ }
}
else
{
- rl78_print_operand_1 (file, XEXP (op, 0), letter);
- fprintf (file, "+");
- rl78_print_operand_1 (file, XEXP (op, 1), letter);
+ if (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && SYMBOL_REF_DECL (XEXP (op, 0))
+ && TREE_CODE (SYMBOL_REF_DECL (XEXP (op, 0))) == FUNCTION_DECL)
+ {
+ fprintf (file, "%%code(");
+ assemble_name (file, rl78_strip_nonasm_name_encoding (XSTR (XEXP (op, 0), 0)));
+ fprintf (file, "+");
+ rl78_print_operand_1 (file, XEXP (op, 1), letter);
+ fprintf (file, ")");
+ }
+ else
+ {
+ rl78_print_operand_1 (file, XEXP (op, 0), letter);
+ fprintf (file, "+");
+ rl78_print_operand_1 (file, XEXP (op, 1), letter);
+ }
}
if (need_paren)
fprintf (file, ")");
@@ -4509,6 +4544,19 @@
return res;
}
+#undef TARGET_PREFERRED_RELOAD_CLASS
+#define TARGET_PREFERRED_RELOAD_CLASS rl78_preferred_reload_class
+
+static reg_class_t
+rl78_preferred_reload_class (rtx x, reg_class_t rclass)
+{
+ if (rclass == NO_REGS)
+ rclass = V_REGS;
+
+ return rclass;
+}
+
+
struct gcc_target targetm = TARGET_INITIALIZER;
#include "gt-rl78.h"
Index: config/rl78/rl78.md
===================================================================
--- config/rl78/rl78.md (revision 222096)
+++ config/rl78/rl78.md (working copy)
@@ -107,7 +107,7 @@
)
(define_expand "eh_return"
- [(match_operand:HI 0 "" "")]
+ [(match_operand:HI 0 "")]
""
"rl78_expand_eh_epilogue (operands[0]);
emit_barrier ();
@@ -169,10 +169,10 @@
;; non-immediate as well.
(define_expand "nonlocal_goto"
[(set (pc)
- (unspec_volatile [(match_operand 0 "" "") ;; fp (ignore)
- (match_operand 1 "" "vi") ;; target
- (match_operand 2 "" "vi") ;; sp
- (match_operand 3 "" "vi") ;; ?
+ (unspec_volatile [(match_operand 0 "") ;; fp (ignore)
+ (match_operand 1 "") ;; target
+ (match_operand 2 "") ;; sp
+ (match_operand 3 "") ;; ?
] UNS_NONLOCAL_GOTO))
]
""
@@ -200,6 +200,14 @@
"
)
+(define_expand "es_addr"
+ [(unspec:SI [(reg:QI ES_REG)
+ (match_operand:HI 0 "")
+ ] UNS_ES_ADDR)]
+ ""
+ ""
+)
+
;;======================================================================
;;
;; "macro" insns - cases where inline chunks of code are more
@@ -243,9 +251,9 @@
)
(define_expand "subsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=&vm")
- (minus:SI (match_operand:SI 1 "general_operand" "vim")
- (match_operand 2 "general_operand" "vim")))
+ [(set (match_operand:SI 0 "nonimmediate_operand")
+ (minus:SI (match_operand:SI 1 "general_operand")
+ (match_operand 2 "general_operand")))
]
""
"emit_insn (gen_subsi3_internal_virt (operands[0], operands[1], operands[2]));
@@ -280,9 +288,9 @@
)
(define_expand "mulqi3"
- [(set (match_operand:QI 0 "register_operand" "")
- (mult:QI (match_operand:QI 1 "general_operand" "")
- (match_operand:QI 2 "nonmemory_operand" "")))
+ [(set (match_operand:QI 0 "register_operand")
+ (mult:QI (match_operand:QI 1 "general_operand")
+ (match_operand:QI 2 "nonmemory_operand")))
]
"" ; mulu supported by all targets
""
@@ -289,9 +297,9 @@
)
(define_expand "mulhi3"
- [(set (match_operand:HI 0 "register_operand" "")
- (mult:HI (match_operand:HI 1 "general_operand" "")
- (match_operand:HI 2 "nonmemory_operand" "")))
+ [(set (match_operand:HI 0 "register_operand")
+ (mult:HI (match_operand:HI 1 "general_operand")
+ (match_operand:HI 2 "nonmemory_operand")))
]
"! RL78_MUL_NONE"
""
@@ -298,8 +306,8 @@
)
(define_expand "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=&v")
- (mult:SI (match_operand:SI 1 "general_operand" "+vim")
+ [(set (match_operand:SI 0 "register_operand" "=&v")
+ (mult:SI (match_operand:SI 1 "general_operand" "vim")
(match_operand:SI 2 "nonmemory_operand" "vi")))
]
"! RL78_MUL_NONE"
@@ -308,7 +316,7 @@
(define_insn "*mulqi3_rl78"
[(set (match_operand:QI 0 "register_operand" "=&v")
- (mult:QI (match_operand:QI 1 "general_operand" "+viU")
+ (mult:QI (match_operand:QI 1 "general_operand" "viU")
(match_operand:QI 2 "general_operand" "vi")))
]
"" ; mulu supported by all targets
@@ -325,7 +333,7 @@
(define_insn "*mulhi3_rl78"
[(set (match_operand:HI 0 "register_operand" "=&v")
- (mult:HI (match_operand:HI 1 "general_operand" "+viU")
+ (mult:HI (match_operand:HI 1 "general_operand" "viU")
(match_operand:HI 2 "general_operand" "vi")))
]
"RL78_MUL_RL78"
@@ -340,7 +348,7 @@
(define_insn "*mulhi3_g13"
[(set (match_operand:HI 0 "register_operand" "=&v")
- (mult:HI (match_operand:HI 1 "general_operand" "+viU")
+ (mult:HI (match_operand:HI 1 "general_operand" "viU")
(match_operand:HI 2 "general_operand" "vi")))
]
"RL78_MUL_G13"
@@ -363,7 +371,7 @@
;; bits of the result).
(define_insn "mulsi3_rl78"
[(set (match_operand:SI 0 "register_operand" "=&v")
- (mult:SI (match_operand:SI 1 "general_operand" "+viU")
+ (mult:SI (match_operand:SI 1 "general_operand" "viU")
(match_operand:SI 2 "general_operand" "vi")))
]
"RL78_MUL_RL78"
@@ -432,12 +440,4 @@
movw %H0, ax
; end of mulsi macro"
[(set_attr "valloc" "macax")]
- )
-
-(define_expand "es_addr"
- [(unspec:SI [(reg:QI ES_REG)
- (match_operand:HI 0 "" "")
- ] UNS_ES_ADDR)]
- ""
- ""
)