RE: [PATCH,WWWDOCS] MIPS changes for GCC 5.0

[Matthew Fortune <Matthew dot Fortune at imgtec dot com>]

Gerald Pfeifer <gerald@pfeifer.com> writes:
> On Thu, 5 Feb 2015, Matthew Fortune wrote:
> > Thanks Catherine. Good call to remove the markup while reviewing. I've
> > done one more pass on this to have the same phrasing used where
> > similar points are being made. I also added a comment about link
> > compatibility for FP64.  Updated text is at the end.
> 
> Here are some more changes on top of the version that was committed.
> 
> Add an article, add markup, simplify language, and use 64-bit instead of
> 64-bits in the MIPS section.
> 
> ("has been changed" -> "has changed", "is being used" -> "is used", and
> there are one or two others which I left since I wasn't sure.)
> 
> I applied this now, though if there is anything you disagree with we can
> always revisit.  Just advise!

Thanks Gerald. This looks fine, just shout if anything else doesn't come
across clearly and I'll try and explain the intent.

Matthew

> 
> Gerald
> 
> Index: changes.html
> ===================================================================
> RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-5/changes.html,v
> retrieving revision 1.104
> diff -u -r1.104 changes.html
> --- changes.html	12 Apr 2015 20:26:50 -0000	1.104
> +++ changes.html	12 Apr 2015 21:32:20 -0000
> @@ -739,13 +739,13 @@
>        <code>-march=p5600</code> command-line option.</li>
>      <li>The Cavium Octeon3 processor is now supported using the
>        <code>-march=octeon3</code> command-line option.</li>
> -    <li>MIPS Release 6 is now supported using <code>-mips32r6</code>
> and
> -      <code>-mips64r6</code> command-line options.</li>
> +    <li>MIPS Release 6 is now supported using the <code>-
> mips32r6</code>
> +       and <code>-mips64r6</code> command-line options.</li>
>      <li>The o32 ABI has been modified and extended.  The o32 64-bit
>        floating-point register support is now obsolete and has been
> removed.
>        It has been replaced by three ABI extensions FPXX, FP64A, and
> FP64.
> -      The meaning of the <code>-mfp64</code> command-line option has
> been
> -      changed and it is now used to enable the FP64A and FP64 ABI
> extensions.
> +      The meaning of the <code>-mfp64</code> command-line option has
> +      changed.  It is now used to enable the FP64A and FP64 ABI
> extensions.
>        <ul>
>  	<li>The FPXX extension requires that code generated to access
>  	    double-precision values use even-numbered registers.  Code that
> @@ -755,14 +755,14 @@
>  	    -mfpxx</code> can be used to enable this extension.  MIPS II is
>  	    the minimum processor required.</li>
>  	<li>The o32 FP64A extension requires that floating-point registers
> be
> -	    64-bits and odd-numbered single-precision registers are not
> +	    64-bit and odd-numbered single-precision registers are not
>  	    allowed.  Code that adheres to the o32 FP64A variant is
>  	    link-compatible with all other o32 double-precision ABI
> variants.
>  	    The command-line options <code>-mabi=32 -mfp64 -mno-odd-spreg
>  	    </code> can be used to enable this extension.  MIPS32R2 is the
>  	    minimum processor required.</li>
>  	<li>The o32 FP64 extension also requires that floating-point
> registers
> -	    be 64-bits, but permits the use of single-precision registers.
> +	    be 64-bit, but permits the use of single-precision registers.
>  	    Code that adheres to the o32 FP64 variant is link-compatible
> with
>  	    o32 FPXX and o32 FP64A variants only, i.e. it is not compatible
>  	    with the original o32 double-precision ABI. The command-line @@
> -777,10 +777,10 @@
>        required to run the generated code on MIPSR5 cores in conjunction
> with
>        future MIPS SIMD (MSA) code and MIPSR6 cores.</li>
>      <li>GCC will now pass all floating-point options to the assembler
> if GNU
> -      binutils 2.25 is being used.  As a result, any inline assembly
> code that
> -      uses hard-float instructions should be amended to include a .set
> -      directive to override the global assembler options when compiling
> for
> -      soft-float targets.</li>
> +      binutils 2.25 is used.  As a result, any inline assembly code
> that
> +      uses hard-float instructions should be amended to include a
> +      <code>.set</code> directive to override the global assembler
> options
> +      when compiling for soft-float targets.</li>
>    </ul>
> 
>  <h3 id="nds32">NDS32</h3>