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Re: [patch] PR rtl-optimization/65220: avoid integer division in stack alignment


On 03/02/2015 10:25 AM, Aldy Hernandez wrote:
> On 03/02/2015 09:55 AM, Richard Henderson wrote:
>> On 02/26/2015 05:46 PM, Aldy Hernandez wrote:
>>> +;; Optimize division or modulo by constant power of 2, if the constant
>>> +;; materializes only after expansion.
>>> +(define_insn_and_split "*udivmod<mode>4_pow2"
>>> +  [(set (match_operand:SWI48 0 "register_operand" "=r")
>>> +    (udiv:SWI48 (match_operand:SWI48 2 "register_operand" "0")
>>> +            (match_operand:SWI48 3 "const_int_operand" "n")))
>>> +   (set (match_operand:SWI48 1 "register_operand" "=r")
>>> +    (umod:SWI48 (match_dup 2) (match_dup 3)))
>>> +   (clobber (reg:CC FLAGS_REG))]
>>> +  "UINTVAL (operands[3]) - 2 < <MODE_SIZE> * BITS_PER_UNIT
>>> +   && (UINTVAL (operands[3]) & (UINTVAL (operands[3]) - 1)) == 0"
>>> +  "#"
>>> +  "reload_completed"
>>> +  [(set (match_dup 1) (match_dup 2))
>>> +   (parallel [(set (match_dup 0) (lshiftrt:<MODE> (match_dup 2) (match_dup
>>> 4)))
>>> +          (clobber (reg:CC FLAGS_REG))])
>>> +   (parallel [(set (match_dup 1) (and:<MODE> (match_dup 1) (match_dup 5)))
>>> +          (clobber (reg:CC FLAGS_REG))])]
>>> +{
>>
>> Do you actually need the reload completed?  Couldn't this be legitimately split
>> before reload (and then parts of it DCE'd as necessary)?
> 
> I think Jakub mentioned we needed it, otherwise we needed to check for a
> division by zero for the INTVAL.  But I could be misunderstanding.

The UINTVAL - 2 < MODE_BIT_SIZE condition means that 0 & 1 are excluded.  So I
don't see how division by zero applies here.


r~


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