This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[RS6000] Fix -m32 -Os lossage


Fixes -Os breakage showing up as 3 testsuite fails like the following,
caused by add<mode>3 losing r0 as a valid source reg.

insn does not satisfy its constraints:
(insn 98 97 99 2 (set (reg:SI 11 11)
        (plus:SI (reg:SI 0 0)
            (const_int 80 [0x50]))) /src/gcc-current/gcc/testsuite/gcc.target/powerpc/savres.c:112 80 {*addsi3}
     (expr_list:REG_DEAD (reg:SI 0 0)
        (nil)))

Bootstrap and regression test in progress.

	* config/rs6000/rs6000.c (rs6000_emit_epilogue): Use addsi3_carry
	or adddi3_carry when restoring frame_reg_rtx from r0 after restvr.

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 220611)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -24977,7 +24977,12 @@ rs6000_emit_epilogue (int sibcall)
 		  rtx offset = GEN_INT (end_save + ptr_off);
 
 		  frame_off = -end_save;
-		  emit_insn (gen_add3_insn (frame_reg_rtx, ptr_reg, offset));
+		  if (TARGET_32BIT)
+		    emit_insn (gen_addsi3_carry (frame_reg_rtx,
+						 ptr_reg, offset));
+		  else
+		    emit_insn (gen_adddi3_carry (frame_reg_rtx,
+						 ptr_reg, offset));
 		}
 	      else
 		{

-- 
Alan Modra
Australia Development Lab, IBM


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]