This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH][rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1
- From: Eric Botcazou <ebotcazou at adacore dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard Sandiford <rdsandiford at googlemail dot com>, Richard Sandiford <richard dot sandiford at arm dot com>, Alan Hayward <Alan dot Hayward at arm dot com>, "steven at gcc dot gnu dot org" <steven at gcc dot gnu dot org>
- Date: Tue, 13 Jan 2015 19:55:55 +0100
- Subject: Re: [PATCH][rtlanal.c][BE][1/2] Fix vector load/stores to not use ld1/st1
- Authentication-results: sourceware.org; auth=none
- References: <D0B07D0D dot 4108%alan dot hayward at arm dot com> <2243996 dot KNkFcg5eZm at polaris> <87a91qg50x dot fsf at googlemail dot com>
> Sorry for the slow response. Jeff has approved the patch in the
> meantime, but I didn't want to go ahead and apply it while there
> was still disagreement...
I still think that it isn't appropriate to short-circuit the main computation
as the patch does, but I don't want to block it after Jeff's approval.
> (1) we have a non-paradoxical subreg;
> (2) both (reg:ymode xregno) and (reg:xmode xregno) occupy full
> hard registers (no padding or unused upper bits);
> (3) (reg:ymode xregno) and (reg:xmode xregno) store the same number
> of bytes (X) in each constituent hard register;
> (4) the offset is a multiple of X, i.e. the data we're accessing
> is aligned to a register boundary; and
> (5) endianness is regular (no differences between words and bytes,
> or between registers and memory)
OK, that's a nice translation of the new code. :-)
It seems to me that the patch wants to extend the support of generic subregs
to modes whose sizes are not multiple of each other, which is a requirement of
the existing code, but does that in a very specific case for the sake of the
ARM port without saying where all the above restrictions come from.
--
Eric Botcazou