Re: [RFC PATCH 3/9] Add TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV target macro

[Vladimir Makarov <vmakarov at redhat dot com>]

On 2014-12-17 8:00 PM, Kaz Kojima wrote:
> This was discussed in PR55212
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c25
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c58
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c69
>
> and is to fix another ICEs in assign_by_spills.
> This patch introduces a new target hook to disable replacing with
> memory equivalence if the macro returns true.
> The problem happens for r0 again.  SH ISA has many instructions with
> "r0-parity".  The index register is r0 only, only r0 can be used as
> QI/HImode load/store target/source, and so on.
> It seems that replacing mem equiv makes register pressure high
> especially on r0 and fails in spilling.  Also replacing mem equiv
> doesn't win CSiBE in average on this target.  Please see the above
> trail #c69 for CSiBE numbers.
>
> I think the one design goal of LRA is to avoid target macros if possible.
> There might be some way to handle the above situation without target
> macros, though it's over my head.

I don't think it will be easy to solve this problem by following reg 
pressure.  I guess R0 will be in the same pressure reg class.  I believe 
some hook is an adequate solution here.

> --
> 	* lra-constraints.c (get_equiv): Don't return memory equivalence
> 	when targetm.cannot_substitute_mem_equiv_p is true.
> 	* target.def (cannot_substitute_mem_equiv_p): New hook.
> 	* config/sh/sh.c (sh_cannot_substitute_mem_equiv_p): New function.
> 	(TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): Define.
> 	* doc/tm.texi.in (TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P): New hook.
> 	* doc/tm.texi: Regenerate.

LRA part of the patch is ok.  I found one typo in "and the speed on 
avarage working sets."  (average).

But I'd recommend to try different hook implementation checking r0 in 
the address as still equiv memory substitution might be profitable for 
SH in some cases.