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Re: [PATCH] Improve prepare_shrink_wrap to sink more instructions
- From: Jiong Wang <jiong dot wang at arm dot com>
- To: Andrew Pinski <pinskia at gmail dot com>
- Cc: Jeff Law <law at redhat dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Thu, 02 Oct 2014 18:37:08 +0100
- Subject: Re: [PATCH] Improve prepare_shrink_wrap to sink more instructions
- Authentication-results: sourceware.org; auth=none
- References: <54087404 dot 1040608 at arm dot com> <540A137A dot 9010402 at redhat dot com> <540DB5CB dot 6080801 at arm dot com> <54120886 dot 30903 at redhat dot com> <5416F8AA dot 7060206 at arm dot com> <541C9563 dot 2050700 at redhat dot com> <CA+=Sn1mJWJin5-tQuWxAoRgDN58k=xbvGPnTWUj9-FZX9CqXew at mail dot gmail dot com>
On 02/10/14 09:49, Andrew Pinski wrote:
On Fri, Sep 19, 2014 at 1:43 PM, Jeff Law <law@redhat.com> wrote:
On 09/15/14 08:33, Jiong Wang wrote:
Jeff,
thanks, I partially understand your meaning here.
take the function "ira_implicitly_set_insn_hard_regs" in ira-lives.c
for example,
when generating address rtl, gcc will automatically generate "const"
operator to prefix
the address expression, like the following. so a simple CONSTANT_P
check is enough in
case there is no embedded register.
(insn 309 310 308 3 (set (reg:DI 44 r15 [orig:94 ivtmp.674 ] [94])
(const:DI (plus:DI (symbol_ref:DI ("recog_data") [flags 0x40]
<var_decl 0x2b2c2ff91510 recog_data>)
(const_int 480 [0x1e0])))) -1
but for architecture like aarch64, the following instruction
sequences to forming address
may be generated
(insn 73 14 74 4 (set (reg/f:DI 20 x20 [99])
(high:DI (symbol_ref:DI ("global_a") [flags 0xc0] <var_decl
0x7ff755a60900 stats>))) 35 {*movdi_aarch64}
(expr_list:REG_EQUIV (high:DI (symbol_ref:DI ("global_a") [flags
0xc0] <var_decl 0x7ff755a60900 stats>))
(nil)))
(insn 17 30 25 5 (set (reg/f:DI 4 x4 [83])
(lo_sum:DI (reg/f:DI 20 x20 [99])
(symbol_ref:DI ("global_a") [flags 0xc0] <var_decl
0x7ff755a60900 stats>))) {add_losym_di}
(expr_list:REG_EQUIV (symbol_ref:DI ("global_a") [flags 0xc0]
<var_decl 0x7ff755a60900 stats>)
(nil)))
while CONSTANT_P could not catch the latter lo_sum case, as the
RTX_CLASS of lo_sum is RTX_OBJ not RTX_CONST_OBJ,
Hmm, it's been ~15 years since I regularly worked on a target that uses
HIGH/LO_SUM, I thought we wrapped the LO_SUM expression inside a CONST as
well, but reading the docs for CONST, that clearly isn't the case.
Could we add a check for lo_sum since it is an RTX_OBJ rather than
RTX_COMM_ARITH or RTX_BIN_ARITH?
thanks, agree, that's exactly what I want to catch, while missed it during the patch re-write. I was been stupid!
anyway, I think we need to solve pr63404, https://gcc.gnu.org/ml/gcc-patches/2014-09/msg02568.html firstly, as it's a correctness regression.
--
Jiong
I am testing the patch for that to fix the above issue. It shows up
with the testcase Jiong added but only with -mabi=ilp32 enabled.
Thanks,
Andrew Pinski
Sorry for that. Can you (re) send your current patch for this for review?
Jeff