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Ping? Patch is attached for easy to apply. Thanks! -Zhenqiang > -----Original Message----- > From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches- > owner@gcc.gnu.org] On Behalf Of Zhenqiang Chen > Sent: Tuesday, July 01, 2014 1:08 PM > To: Richard Earnshaw > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [PATCH, 2/10] prepare ccmp > > On 25 June 2014 22:41, Richard Earnshaw <rearnsha@arm.com> wrote: > > On 23/06/14 07:57, Zhenqiang Chen wrote: > >> Hi, > >> > >> The patch makes several functions global, which will be used when > >> expanding ccmp instructions. > >> > >> The other change in this patch is to check CCMP when turning code > >> into jumpy sequence. > >> > >> OK for trunk? > >> > > > > This isn't a complete review. In particular, I'd like one of the > > gimple experts to go over this again. > > > > However, some general issues do crop up. I'll deal with each patch as > > I spot something. > > > > > > enum rtx_code code; > >> @@ -6503,6 +6503,12 @@ get_rtx_code (enum tree_code tcode, bool > unsignedp) > >> code = LTGT; > >> break; > >> > >> + case BIT_AND_EXPR: > >> + code = AND; > >> + break; > >> + case BIT_IOR_EXPR: > >> + code = IOR; > >> + break; > > > > Blank lines between case alternatives. > > Thanks. Patch is updated. > > diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index e8cd87f..a32e1b3 > 100644 > --- a/gcc/cfgexpand.c > +++ b/gcc/cfgexpand.c > @@ -2095,9 +2095,10 @@ expand_gimple_cond (basic_block bb, gimple > stmt) > op0 = gimple_assign_rhs1 (second); > op1 = gimple_assign_rhs2 (second); > } > - /* If jumps are cheap turn some more codes into > - jumpy sequences. */ > - else if (BRANCH_COST (optimize_insn_for_speed_p (), false) < 4) > + /* If jumps are cheap and the target does not support conditional > + compare, turn some more codes into jumpy sequences. */ > + else if (BRANCH_COST (optimize_insn_for_speed_p (), false) < 4 > + && (targetm.gen_ccmp_first == NULL)) > { > if ((code2 == BIT_AND_EXPR > && TYPE_PRECISION (TREE_TYPE (op0)) == 1 diff --git > a/gcc/expmed.c b/gcc/expmed.c index e76b6fc..c8d63a9 100644 > --- a/gcc/expmed.c > +++ b/gcc/expmed.c > @@ -5105,7 +5105,7 @@ expand_and (enum machine_mode mode, rtx op0, > rtx op1, rtx target) } > > /* Helper function for emit_store_flag. */ -static rtx > +rtx > emit_cstore (rtx target, enum insn_code icode, enum rtx_code code, > enum machine_mode mode, enum machine_mode compare_mode, > int unsignedp, rtx x, rtx y, int normalizep, diff --git a/gcc/expmed.h > b/gcc/expmed.h index 4d01d1f..a567bad 100644 > --- a/gcc/expmed.h > +++ b/gcc/expmed.h > @@ -20,6 +20,8 @@ along with GCC; see the file COPYING3. If not see > #ifndef EXPMED_H #define EXPMED_H 1 > > +#include "insn-codes.h" > + > enum alg_code { > alg_unknown, > alg_zero, > @@ -665,4 +667,9 @@ convert_cost (enum machine_mode to_mode, enum > machine_mode from_mode, } > > extern int mult_by_coeff_cost (HOST_WIDE_INT, enum machine_mode, > bool); > + > +extern rtx emit_cstore (rtx target, enum insn_code icode, enum rtx_code > code, > + enum machine_mode mode, enum machine_mode > compare_mode, > + int unsignedp, rtx x, rtx y, int normalizep, > + enum machine_mode target_mode); > #endif > diff --git a/gcc/expr.c b/gcc/expr.c > index 512c024..04cf56e 100644 > --- a/gcc/expr.c > +++ b/gcc/expr.c > @@ -146,8 +146,6 @@ static rtx store_field (rtx, HOST_WIDE_INT, > HOST_WIDE_INT, static unsigned HOST_WIDE_INT > highest_pow2_factor_for_target (const_tree, const_tree); > > static int is_aligning_offset (const_tree, const_tree); -static void > expand_operands (tree, tree, rtx, rtx*, rtx*, > - enum expand_modifier); > static rtx reduce_to_bit_field_precision (rtx, rtx, tree); static rtx > do_store_flag (sepops, rtx, enum machine_mode); #ifdef > PUSH_ROUNDING @@ -7496,7 +7494,7 @@ convert_tree_comp_to_rtx > (enum tree_code tcode, int unsignedp) > The value may be stored in TARGET if TARGET is nonzero. The > MODIFIER argument is as documented by expand_expr. */ > > -static void > +void > expand_operands (tree exp0, tree exp1, rtx target, rtx *op0, rtx *op1, > enum expand_modifier modifier) { diff --git a/gcc/expr.h > b/gcc/expr.h index 6a1d3ab..66ca82f 100644 > --- a/gcc/expr.h > +++ b/gcc/expr.h > @@ -787,4 +787,6 @@ extern bool categorize_ctor_elements (const_tree, > HOST_WIDE_INT *, > by EXP. This does not include any offset in DECL_FIELD_BIT_OFFSET. */ > extern tree component_ref_field_offset (tree); > > +extern void expand_operands (tree, tree, rtx, rtx*, rtx*, > + enum expand_modifier); > #endif /* GCC_EXPR_H */ > diff --git a/gcc/optabs.c b/gcc/optabs.c index ca1c194..0c3dae1 100644 > --- a/gcc/optabs.c > +++ b/gcc/optabs.c > @@ -6453,7 +6453,7 @@ gen_cond_trap (enum rtx_code code, rtx op1, rtx > op2, rtx tcode) > /* Return rtx code for TCODE. Use UNSIGNEDP to select signed > or unsigned operation code. */ > > -static enum rtx_code > +enum rtx_code > get_rtx_code (enum tree_code tcode, bool unsignedp) { > enum rtx_code code; > @@ -6503,6 +6503,14 @@ get_rtx_code (enum tree_code tcode, bool > unsignedp) > code = LTGT; > break; > > + case BIT_AND_EXPR: > + code = AND; > + break; > + > + case BIT_IOR_EXPR: > + code = IOR; > + break; > + > default: > gcc_unreachable (); > } > diff --git a/gcc/optabs.h b/gcc/optabs.h index 089b15a..61be4e2 100644 > --- a/gcc/optabs.h > +++ b/gcc/optabs.h > @@ -91,6 +91,7 @@ extern rtx expand_widen_pattern_expr (sepops ops, > rtx op0, rtx op1, rtx wide_op, extern rtx expand_ternary_op (enum > machine_mode mode, optab ternary_optab, > rtx op0, rtx op1, rtx op2, rtx target, > int unsignedp); > +extern enum rtx_code get_rtx_code (enum tree_code tcode, bool > +unsignedp); > > /* Expand a binary operation given optab and rtx operands. */ extern rtx > expand_binop (enum machine_mode, optab, rtx, rtx, rtx, int,
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