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[PATCH i386 AVX512] [39/n] Extend ashrv insn patterns.
- From: Kirill Yukhin <kirill dot yukhin at gmail dot com>
- To: Uros Bizjak <ubizjak at gmail dot com>
- Cc: Jakub Jelinek <jakub at redhat dot com>, Richard Henderson <rth at redhat dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, kirill dot yukhin at gmail dot com
- Date: Fri, 12 Sep 2014 17:45:59 +0400
- Subject: [PATCH i386 AVX512] [39/n] Extend ashrv insn patterns.
- Authentication-results: sourceware.org; auth=none
Hello,
Patch in the bottom (derived with git diff -w)
extends ashrv insns patterns.
I choosen to add `_1' to `VI24_AVX512BW_1' mode iterator
because of it is irregular.
Bootstrapped.
AVX-512* tests on top of patch-set all pass
under simulator.
Is it ok for trunk?
gcc/
* config/i386/sse.md (define_mode_iterator VI248_AVX512BW_AVX512VL):
New.
(define_mode_iterator VI24_AVX512BW_1): Ditto.
(define_insn "<mask_codefor>ashr<mode>3<mask_name>"): Ditto.
(define_insn "<mask_codefor>ashrv2di3<mask_name>"): Ditto.
(define_insn "ashr<VI248_AVX512BW_AVX512VL:mode>3<mask_name>"): Update
mode iterator.
(define_expand "ashrv2di3"): Update to enable TARGET_AVX512VL.
--
Thanks, K
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 73bdd22..b5ded79 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -382,6 +382,15 @@
(V8SI "TARGET_AVX2") V4SI
(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX2") V2DI])
+(define_mode_iterator VI248_AVX512BW_AVX512VL
+ [(V32HI "TARGET_AVX512BW")
+ (V4DI "TARGET_AVX512VL") V16SI V8DI])
+
+;; Suppose TARGET_AVX512VL as baseline
+(define_mode_iterator VI24_AVX512BW_1
+ [(V16HI "TARGET_AVX512BW") (V8HI "TARGET_AVX512BW")
+ V8SI V4SI])
+
(define_mode_iterator VI48_AVX512F
[(V16SI "TARGET_AVX512F") V8SI V4SI
(V8DI "TARGET_AVX512F") V4DI V2DI])
@@ -9282,12 +9291,40 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<sseinsnmode>")])
+(define_insn "<mask_codefor>ashr<mode>3<mask_name>"
+ [(set (match_operand:VI24_AVX512BW_1 0 "register_operand" "=v,v")
+ (ashiftrt:VI24_AVX512BW_1
+ (match_operand:VI24_AVX512BW_1 1 "nonimmediate_operand" "v,vm")
+ (match_operand:SI 2 "nonmemory_operand" "v,N")))]
+ "TARGET_AVX512VL"
+ "vpsra<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "type" "sseishft")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand")
+ (const_string "1")
+ (const_string "0")))
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "<mask_codefor>ashrv2di3<mask_name>"
+ [(set (match_operand:V2DI 0 "register_operand" "=v,v")
+ (ashiftrt:V2DI
+ (match_operand:V2DI 1 "nonimmediate_operand" "v,vm")
+ (match_operand:DI 2 "nonmemory_operand" "v,N")))]
+ "TARGET_AVX512VL"
+ "vpsraq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
+ [(set_attr "type" "sseishft")
+ (set (attr "length_immediate")
+ (if_then_else (match_operand 2 "const_int_operand")
+ (const_string "1")
+ (const_string "0")))
+ (set_attr "mode" "TI")])
+
(define_insn "ashr<mode>3<mask_name>"
- [(set (match_operand:VI48_512 0 "register_operand" "=v,v")
- (ashiftrt:VI48_512
- (match_operand:VI48_512 1 "nonimmediate_operand" "v,vm")
+ [(set (match_operand:VI248_AVX512BW_AVX512VL 0 "register_operand" "=v,v")
+ (ashiftrt:VI248_AVX512BW_AVX512VL
+ (match_operand:VI248_AVX512BW_AVX512VL 1 "nonimmediate_operand" "v,vm")
(match_operand:SI 2 "nonmemory_operand" "v,N")))]
- "TARGET_AVX512F && <mask_mode512bit_condition>"
+ "TARGET_AVX512F"
"vpsra<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseishft")
(set (attr "length_immediate")
@@ -14912,7 +14949,9 @@
(ashiftrt:V2DI
(match_operand:V2DI 1 "register_operand")
(match_operand:DI 2 "nonmemory_operand")))]
- "TARGET_XOP"
+ "TARGET_XOP || TARGET_AVX512VL"
+{
+ if (!TARGET_AVX512VL)
{
rtx reg = gen_reg_rtx (V2DImode);
rtx par;
@@ -14935,6 +14974,7 @@
emit_insn (gen_xop_shav2di3 (operands[0], operands[1], reg));
DONE;
+ }
})
;; XOP FRCZ support