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Re: [PATCH ARM]memset inlining patch for arm
- From: Ramana Radhakrishnan <ramana dot gcc at googlemail dot com>
- To: "Bin.Cheng" <amker dot cheng at gmail dot com>
- Cc: Richard Earnshaw <rearnsha at arm dot com>, Bin Cheng <bin dot cheng at arm dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 10 Sep 2014 09:52:57 +0100
- Subject: Re: [PATCH ARM]memset inlining patch for arm
- Authentication-results: sourceware.org; auth=none
- References: <000801cfc806$a0add6e0$e20984a0$ at arm dot com> <540EDB4D dot 4050501 at arm dot com> <CAHFci2_1h4TwSKWjKsN08hbL3W7n9Qt9qi1ieDs2AEKxuq+DSg at mail dot gmail dot com>
- Reply-to: ramrad01 at arm dot com
On Wed, Sep 10, 2014 at 9:16 AM, Bin.Cheng <amker.cheng@gmail.com> wrote:
> On Tue, Sep 9, 2014 at 6:49 PM, Richard Earnshaw <rearnsha@arm.com> wrote:
>> On 04/09/14 07:08, Bin Cheng wrote:
>>> @@ -1872,7 +1892,9 @@ const struct tune_params arm_cortex_a53_tune =
>>> {true, true}, /* Prefer non short circuit. */
>>> &arm_default_vec_cost, /* Vectorizer costs. */
>>> false, /* Prefer Neon for 64-bits bitops. */
>>> - false, false /* Prefer 32-bit encodings. */
>>> + false, false, /* Prefer 32-bit encodings. */
>>> + false, /* Prefer Neon for stringops. */
>>> + 8 /* Maximum insns to inline memset. */
>>> };
>>>
>>> const struct tune_params arm_cortex_a57_tune =
>>> @@ -1889,7 +1911,9 @@ const struct tune_params arm_cortex_a57_tune =
>>> {true, true}, /* Prefer non short circuit. */
>>> &arm_default_vec_cost, /* Vectorizer costs. */
>>> false, /* Prefer Neon for 64-bits bitops. */
>>> - true, true /* Prefer 32-bit encodings. */
>>> + true, true, /* Prefer 32-bit encodings. */
>>> + false, /* Prefer Neon for stringops. */
>>> + 8 /* Maximum insns to inline memset. */
>>> };
>>
>> Why don't we use Neon for Cortex-(A53,A57)? We've used it for
>> Cortex-(A7,A8,A15).
> Hi Richard,
>
> Since changes in aarch64.md is needed, also the bug and patch are for
> arm only, I left this behind for aarch64. Another aarch64 patch
> should be worked for this in the near (?) future.
We should fix that up. Cortex-A57 and Cortex-A53 can run AArch32 code,
that's why you have that support in the ARM backend.
Ramana
>
> Thanks,
> bin