This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[Patch AArch64] Fix for PR62262


Hi

In insn pattern "*andim_ashift<mode>_bfiz", if the operands[2] is larger than
the size of register, gcc may generate invalid assembler code. If operands[2]
is larger than the size of the underlying type of INTVAL, the following insn
condition may also be undefined.

"exact_log2 ((INTVAL (operands[3]) >> INTVAL (operands[2])) + 1) >= 0
 && (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0"

It can be fixed by checking the value of operands[2] before using it.

Passed regression test without failure. OK for trunk and 4.9 branch?

thanks
Guozhi Wei


2014-08-26  Guozhi Wei  <carrot@google.com>

        PR target/62262
        * config/aarch64/aarch64.md (*andim_ashift<mode>_bfiz): Check the shift
        amount before using it.


2014-08-26  Guozhi Wei  <carrot@google.com>

        PR target/62262
        * gcc.target/aarch64/pr62262.c: New test.

Attachment: patch
Description: Binary data


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]