Re: [PATCH AArch64 3/3] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EON

[Kugan <kugan dot vivekanandarajah at linaro dot org>]

On 13/08/14 00:55, Alan Lawrence wrote:
> ...patch attached...
> 
> Alan Lawrence wrote:
>> [When I wrote that xor was broken on GPRs and this fixes it, I meant
>> xor_one_cmpl rather than xor, sorry!]
>>
>> The pattern for xor_one_cmpl never matched, due to the action of
>> combine_simplify_rtx; hence, separate this pattern out from that for
>> ORN/BIC.
>>
>> ORN/BIC have equivalent SIMD-reg variants, so add those for the
>> benefit of values in vector registers (e.g. passed as [u]int64x1_t
>> parameters).
>>
>> EON does not have a SIMD-reg variant; however, it seems better to
>> split it (to XOR + NOT) than to move both arguments to GPRs, perform
>> EON, and move the result back.
>>


+;; (xor (not a) b) is simplify_rtx-ed down to (not (xor a b)).
+;; eon does not operate on SIMD registers so the vector variant must be
split.
+(define_insn_and_split "*xor_one_cmpl<mode>3"
+  [(set (match_operand:GPI 0 "register_operand" "=r,w")
+        (not:GPI (xor:GPI (match_operand:GPI 1 "register_operand" "r,?w")

Hi Alan,

Is there any specific reason for why you are disparaging slightly this
alternative  with ‘?’. Your earlier patch removes '!' from subdi3.

Thanks,
Kugan


+                          (match_operand:GPI 2 "register_operand"
"r,w"))))]
+  ""
+  "eon\\t%<w>0, %<w>1, %<w>2" ;; For GPR registers (only).
+  "reload_completed && (which_alternative == 1)" ;; For SIMD registers.
+  [(set (match_operand:GPI 0 "register_operand" "=w")
+        (xor:GPI (match_operand:GPI 1 "register_operand" "w")
+                 (match_operand:GPI 2 "register_operand" "w")))
+   (set (match_dup 0) (not:GPI (match_dup 0)))]